MIPI to DP bridge IC.

Hi,

Would DSI86 be a fit for your application?

Thanks

David

Hi,

Stream bit rate = pixel clock * bpp = 483.12 * 30 = 14493.6

Min DSI clock = stream bit rate / 2 * DSI lanes, assumes 8 DSI lanes, Min DSI clock = 905.85MHz

Unfortunately this resolution is outside the DSI86 DSI clock (max 750MHz) support range.

Thanks

David

Thank you for your comments.

Any solution for converter ic supporting  QHD@120, 10bit ? DP or HDMI? 

Hi,

Unfortunately we do not have a device that can support higher bandwidth.

Thanks

David