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XIO3130: XIO3130 PCI Express Packet Switch Silicon Errata

Noriyuki Takahashi
Genius 9245 points
Part Number: XIO3130

Hi team

There is a question about the errata, especially for "2. When operating in normal mode, the downstream resets (DNx_PERST#) will de-assert before the downstream reference clock is stable (PG2.0, PG2.1)"

https://www.tij.co.jp/jp/lit/er/sllz071a/sllz071a.pdf?ts=1632286624660&ref_url=https%253A%252F%252Fwww.tij.co.jp%252Fproduct%252Fjp%252FXIO3130

If we follow the workaround, the reset time for the Host may be shorter than the reset time for slaves. And this can cause the host can't recognize slaves, because slaves are still under reset condition.

In order to solve this, the host should wait for enough time, so that slaves can work properly. 

Could you tell other ways to solve it except for waiting for enough time?

Regards,

Noriyuki Takahashi