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DS90LV012A: AC coupled CML input requirements

Part Number: DS90LV012A

Hi I'm using the DS90LV012A as a CML receiver. My input is currently AC coupled and terminated with a 100 Ohm R between inputs. Do I require anything other biasing on the input side?  Another thread on this part makes reference to and mentions to refer to Figures 18 and 19. Both are AC coupled CML to LVDS however Figure 18 is for internally self biased and Figure 19 assumes an internally generated bias voltage pin (VBB). The DS90LV012A doesn't have a VBB pin.

1. Is it safe to assume, since TI referenced this document, that the part is self biased and that no external biasing is needed to create the common mode?


2. Are the 3V3 10k divider in Figure 18,page 11, there to ensure the inputs aren't floating when no driver is attached? Are these necessary?

3. The notes in the DS for the DS90LV012A  around the electrical parameters of VCM and VID, Note 3, are difficult to understand what the accepted range is. It mentions: . VID is not allowed to be greater than 100 mV when VCM = 0.05V to 2.35V when VDD = 2.7V or when VCM = |VID| / 2 to VDD − 0.3V when VDD = 3.0V to 3.6V

Which to me seems to indicate that VID can only be above 100mV if VCM is < 50mV for VDD = 2.7V or 3.3V...

But then later they show a test pattern of VCM = 1.2V and 200mV VID... I know the LVDS spec is 100mV to 600mV VID with 1.2V VCM so what am i missing :)  ?



  • Adam

    The resistor divider network provides biasing on the negative input terminal. The positive input terminal will also get the common mode voltage through the 100-Ω termination. With this approach, there will be some differential skew between the positive and negative input terminals.

    For AC coupling, please also make sure the data is properly DC balanced.