DS90UH941AS-Q1: DSI CLK difference info in ALP

Hi Roy,

The 200 Mhz you are reading is the PCLK and not the DSI clock. This reading will be a little off from your actual PCLK value because it is meant to only be used for debug mode.

Is your 941AS in dual mode or single mode?

Regards,

Michael W.

Hi Michael,

941 is working in dual mode. 

I'm note sure the relationship between DSI CLK and PCLK. Do we have related document or FAQ can be shared?

Roy

Hi Roy,

Is this the block diagram for your system? The PCLK frequency is going to be the (DSI clock frequency) / 3 if you are using 4 lane DSI and one DSI port input. if you are using DSI dual the PCLK = 2*(DSI clock frequency) / 3.

Regards,

Michael W.

Hi Michael,

Thanks for information. But the result has conflict. In my application. DSI CLK is 92MHz for each port. The ALP showed the PCLK = 200MHz. 

How can we explain the result?

Roy

Hi Michael,

Above issue was fixed. Now we are facing another issue. Now we use external DSI to bring up the display, but we find the link between 941 <-> 984 will lost.

Link Ready sometimes gets True and sometime get False, but most of time is False. Can you let me know the possible root cause? Or any register that we forgot to set?

And we had used 941 internal Patgen to bring up the display successfully. The link was stable. 

Regards,

Roy

Hi Roy,

Can you get me a reg dump of the 941 when the link is lost and when it is stable?

Regards,

Michael W.

Hi Michael,

Please see this for 941 register content. It's hard to get link stable register because the link is stable < 1s

Roy Chou1 said:

auo dsi display.nrd

Roy

Hi Roy,

I see that, did you modify anything between this register dump and your current system? What is your DSI source SOC?

Regards,

Michael W.

Hi Michael,

They used the signal generator to generate the desired DSI signal. They had verified the signal was ok in another project. Below are the register dump when we used external DSI and 941internal Patgen. Per talked, in external DSI mode, FPD link status is False. In addition, lock pin on 984 was also on low level. 

auo dsi display.zip

auo pattern generator display.zip

Regards.

Roy

Hi Roy,

The 941AS has an very tight skew requirement between the DSI ports the requirement is that the " Skew between DSI ports must be less than two pixel clock periods (single DSI pixel clock frequency)" . I suspect that this is causing the issue, can you verify that your DSI source can meet this requirement?

Regards,

Michael W.