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DS90UB927Q-Q1: LVDS data to clock frequency ratio?

Part Number: DS90UB927Q-Q1
Other Parts Discussed in Thread: AWR1642

I have a radar application using the AWR1642.  Aptiv would like to  use the AWR1642 LVDS interface to a FPDLink device in production.  I would really like to make this work as it is very high volume. The closest device that I can find is the DS90UB927. 

What are the options for data to clock ratio?

How is data clocked in since the clock only transitions every x many data bits?

Is blanking times required?

Any other issues to watch out for?

  • Hi,

    The LVDS has only one data to clock ratio. the ratio is data 7 bits for every clock cycle.

    This diagram shows the relationship between LVDS data and clock.

    FPD-Link III requires blanking to be included in the video data.

    you must also make sure that the AWR1642 can output the correct voltage levels.


    Michael W.

  • Michael,

    What about the case of the checkerboard pattern in figure 8 of the datasheet?  It appears to be a different than 7x rate.  Is there any backwards compatibility mode that I might be able to get to work?  Any other ideas?

  • Hi Mike,

    Sorry, I was incorrect before the FPD-Link III does not require blanking on the input video unless you are using audio or HDCP. So you can video into and out of the 927 without blanking. 

    Looking closer at the AWR1642, the LVDS interface will not be compatible with the 927, due to the relationship between the clock rate and data rate.


    Michael W.