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TSER953: CSI-2 Errors

Luis Villaran
Prodigy 80 points
Part Number: TSER953
Other Parts Discussed in Thread: TDES954

I have a TDES954 and a TSER953 setup with a coax connection, and the V3Link connection seems stable -- I'm able to talk to both chipsets, toggle GPIOs, etc.  I have the TSER953 connected to an OV2740 sensor with two data lanes and the connections are very short on the board.  I'm getting CSI-2 errors -- namely the reading from register 0x5E I'm reading 0x44, which is "Lane 0/1: Multi-bit Error in SYNC Sequence - Uncorrectable".  That error sounds pretty bad, but I'm wondering A) what could cause it and B) if this is truly uncorrectable (i.e. there's something fundamentally wrong) or if that just means the chip is unable to correct it, but it may be correctable with a change of passives or something along those lines.

Thanks,

luis

  • 0
    TI__Guru* 83730 points

    Hello Luis,

    SOT Sync Errors are errors with the start of transmission. In the MIPI standard, the D-PHY TX sends a sync sequence as part of the HS start of transmission sequence. You may want to verify the signal integrity from your D-PHY CSI TX (Imager) to the TSER953 and also verify your TX is not having issues. The D-PHY standard sync sequence is " ‘00011101’ beginning on a rising Clock edge". You can probe the signal and make sure that the TX is outputting this sequence.

    Question; If you read 0x5D, does it clear?

  • +1 in reply to Hamzeh Jaradat
    Prodigy 80 points

    reading 0x5D does not clear it, but layout issues were found that keep this board from working. thanks for your help anyway!