TCA9539-Q1: What is the GPIO output state when I2C communication is abnormal disrupted?

HAIBIN MA

Prodigy 50 points

Part Number: TCA9539-Q1
Other Parts Discussed in Thread: TCA9539,

Dear Expert，

I want to know when the TCA9539's I2C is disrupted, the GPIO will remain output level or reset to the power-on state?

Thanks!

over 2 years ago

0 Tyler Townsend over 2 years ago

TI__Mastermind 23843 points

Haibin,

In the event of a time-out or improper operation, the system controller can reset the TCA9549-Q1 by asserting an active low input to the RESET input. This will put registers back to their default state setting I/O's to inputs and initializing the I2C-SMBus state machine.

Regards,

Tyler

0 HAIBIN MA over 2 years ago in reply to Tyler Townsend

Prodigy 50 points

Hi Tyler,

Yes, I know your mean. But I want to know is when the system controller was run abnormal lead to the I2C bus abnormal, what will be the I/O's state?

0 Clemens Ladisch over 2 years ago in reply to HAIBIN MA

Guru 244200 points

The output pins will change only at the ACK bit (that is, at the 27th or 36th clock edge) at the end of the register write (see figure 8-9).

A STOP condition will end the transaction. If the STOP condition is corrupted, the following clock cycles might be seen by the TCA9539-Q1 as the last part of the write transaction.

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TCA9539-Q1: What is the GPIO output state when I2C communication is abnormal disrupted?