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[FAQ] DS90UB941AS-Q1: DSI or REFCLK Jitter Measurement

Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: DS90UH941AS-Q1

For the DS90UB941AS-Q1 or DS90UH941AS-Q1 serializer devices, what is the measurement methodology for DSI or REFCLK input jitter?

  • The jitter requirements for DS90UB941-Q1/DS90UH941AS-Q1 depend on the operating mode that the device is used in. The main two modes to consider are:

    - DSI Reference Clock Mode - The DSI clock from the video source is used as the reference clock for the serializer device. No external oscillator or crystal input is needed to the serializer

    - External REFCLK mode - The DSI clock is only used for clocking the video inputs to the device but is not used as the reference clock for the serializer. In this mode, an external REFCLK must be connected to the serializer REFCLK inputs at the same frequency as the pixel clock for the video 

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    In DSI Reference Clock Mode, the DSI clock input jitter requirement is critical, since the DSI clock is used to source the clock for the FPD III serializer which operates at much higher speed than the DSI input.

    In single FPD-Link III mode, the FPD-Link rate is fDSI*(N/12)*35, where N is the number of DSI lanes and fDSI is the DSI clock frequency in MHz. 

    In dual FPD-Link III mode, the FPD-Link rate is fDSI*(N/12)*(35/2) per FPD-Link lane 

    Since the FPD-Link III UI is much smaller than the UI of the DSI clock, jitter contribution from the DSI clock impacts the jitter of the FPD III clock proportionally, and thus the DSI clock jitter is specified in terms of the FPD3 UI instead of the DSI clock UI. The requirement for DSI clock jitter in this mode is:

    For example, with a PCLK of 148.5MHz, dual FPD-Link, and using 4 DSI lanes, the fDSI would be 148.5*(12/4) = 445.5MHz. The DSI clock jitter requirement would be:

    (1/(35*148.5MHz/2))*0.3 = 115ps

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    In External Reference Clock Mode, the DSI clock jitter does not have a timing requirement related directly to the FPD III UI, since it is not used for sourcing the FPD III clock directly. The DSI clock requirements in External Reference Clock Mode are based only on the standard timing requirements from the MIPI DPHY specification. In this mode, the REFCLK input jitter should be characterized according to the datasheet requirement:

    For example, with a PCLK of 148.5MHz, dual FPD-Link, and using 4 DSI lanes, the fDSI would be 148.5*(12/4) = 445.5MHz. The External REFCLK frequency is 148.5MHz, and the REFCLK clock jitter requirement would be:

    (1/(35*148.5MHz/2))*0.28 = 108ps

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    The DS90UB941AS-Q1/DS90UH941AS-Q1 jitter requirements are for Total Jitter (TJ@BER): https://www.ti.com/lit/pdf/SCAA120B 

    To characterize total jitter, TI recommends to measure the TJ@BER with a high speed oscilloscope equipped with a jitter analysis program such as DPOJET. The clock recovery settings used in the DPOJET measurement are designed to match the input PLL characteristic of the serializer device:

    - Method = PLL Custom BW 

    - PLL Type = Type II

    - Loop BW = f/40 for dual FPD-Link (where f = PCLK)

    - Loop BW = f/20 for single FPD-Link (where f = PCLK)

    - Damping = 2

    - Target BER = 1e-10