TCAN1145-Q1: max SPI rate in sleep mode and the conditions

Hi Eric-san,
Thank you for your answer.
I have  some questions.

1) The 10us delay means time  between pulling nCS low and the start of a read or write.  Where is the start of a read or write?  Is it the first up-edge of CLK ?

2)  It seems that INT_2 bit of INT_GLOBAL register (50h) is set just after reset, because the INT_2 bit is logical OR of INT_2 register which includes PWRON bit which is set to 1 just after reset., but datasheet describes that the INT_2 bit is cleared just after reset.  Which is correct, INT_2=0, or 1 just after reset?  If PWRON =1, INT_2 is always 1?

3) SMS bit of INT_2 register is related to UVIO timeout and UVIO + TSD.  What is the assumed situation of UVIO timeout and UVIO + TSD?

4) Both SWE timer and tinactive timer is described in datasheet.  Are they same meaning?

5) The following recognition for state transition is correct?
     1. If SWE timer is expired in fail safe mode, the state moves to sleep mode.
     2. When any fault is cleared within Tinactive, 
          a. if wakeup is detected,  the state is moved to Standby mode.
          b.  The state is moved to Standby mode, Normal mode, Listen Mode by SPI command.

6) In the above situation,  can user confirm whether fault is cleared or not, by readback UVIO, UVCC, or TSD bit in INT_2 register?

7) If user want to move to sleep mode quickly after detecting fault, Fail safe mode should be disable?
     If user want to detect the fault for a while, users should enable Fail safe mode?

8) What is the meaning of  PWRON in INT_2 register?

Best Regards, Taki

Takigasaki-san,

1) The 10us delay means time  between pulling nCS low and the start of a read or write.  Where is the start of a read or write?  Is it the first up-edge of CLK ?

It is the minimum amount of time before the SPI receiver can interpret SPI reads or writes. So it is both when the first rising edge of the SCLK can be used to shift data in, and the moment at which SDI can begin sending data/SDO can begin sampling and reading data.

2)  It seems that INT_2 bit of INT_GLOBAL register (50h) is set just after reset, because the INT_2 bit is logical OR of INT_2 register which includes PWRON bit which is set to 1 just after reset., but datasheet describes that the INT_2 bit is cleared just after reset.  Which is correct, INT_2=0, or 1 just after reset?  If PWRON =1, INT_2 is always 1?

You are correct, the PWRON flag will always be 1 after a reset, as this is the interrupt indicating a power-on reset has occurred. This would mean that on every reset, INT_2 should be a 1, and the table in the datasheet indicating a 1 on reset is incorrect. I'm in the process of updating this datasheet and will add this to my list of edits.

3) SMS bit of INT_2 register is related to UVIO timeout and UVIO + TSD.  What is the assumed situation of UVIO timeout and UVIO + TSD?

The flag is related to UVIO timeout OR UVIO + TSD, not both. UVIO timeout is referring to the tUV timer running out, while UVIO + TSD refers to UVIO first being detected plus a thermal shutdown condition occurring at the same time.

4) Both SWE timer and tinactive timer is described in datasheet.  Are they same meaning?

Kind of, tinactive is the actual time parameter and how long the SWE timer lasts. The SWE timer is triggered by default by tsilent and when the CANSLNT flag is asserted. SWE timer is turned on and after 4 minutes will automatically put the device into a sleep state unless the CANSLNT flag is cleared. There are other control bits that allow for the SWE timer to be disabled, or reset on CAN traffic, and these bits are located in register 0x1C.

5) The following recognition for state transition is correct?
     1. If SWE timer is expired in fail safe mode, the state moves to sleep mode.

        That is correct.
     2. When any fault is cleared within Tinactive, 
          a. if wakeup is detected,  the state is moved to Standby mode.

              Correct, the SWE timer can also be disabled so that the device won't go into sleep mode if tinactive expires.
          b.  The state is moved to Standby mode, Normal mode, Listen Mode by SPI command.

              Correct, this is true in any case unless a fault is keeping the device in failsafe mode.

6) In the above situation,  can user confirm whether fault is cleared or not, by readback UVIO, UVCC, or TSD bit in INT_2 register?

Yes, the best way to do this is to read all interrupt registers, clear them, then read again to see if they stay cleared. This will indicate whether the fault condition is still present or not.

7) If user want to move to sleep mode quickly after detecting fault, Fail safe mode should be disable?

That is correct. Once the fault cases are detected, the device will go into sleep mode if failsafe mode is disabled.
     If user want to detect the fault for a while, users should enable Fail safe mode?

The user could still detect the fault for a while in sleep mode unless it's a UVIO condition. VIO is needed for SPI communication.

8) What is the meaning of  PWRON in INT_2 register?

This interrupt is triggered if a hard reset occurs or the Supply on VSUP threshold is surpassed.

Please let me know if you have any other questions.

Regards,

Eric Hackett 

Eric-san,
Thank you for your reply.

- Rerated to your answer for Q2)  in above, you mentioned that the table in the datasheet indicating a 1 on reset is incorrect.
  Where, the table indicating "0" in current version of the datasheet as shown in below, but it's incorrect.  Is my understanding correct?  

- Should user clear PWRON flag manually after reset to detect next reset? 

- Related to your answer for Q3), What is the reason why we have to care about UVIO+TSD condition?  

Best Regards, Taki

Takigasaki-san,

Sorry for the confusion, the fact that INT_2 says 0b on reset is incorrect, as it currently is in the datasheet. It should say 1 from my experience. I'm going to verify this with our digital design team then update the datasheet accordingly.

Yes, the user should clear the PWRON flag manually after reset, otherwise the PWRON flag will stay asserted, it does not clear on its own.

If a UVIO condition is present and the TSD flag is also asserted, this means that there is a very fast rise in temperature on the silicon, and if it continues to rise at the same rate, there could be damage as a result. This could be a case where a strong supply is being used for VIO and it gets shorted to GND, dissipating a lot of power from the supply to the TCAN114x-Q1 transceiver.

Regards,

Eric Hackett