SN75LVDS387: LVCMOS input rather than LVTTL?

Hi,

Are you referring to 3.3V, 2.5V, or 1.8V LVCMOS?

Referring to this chart below, the 3.3V LVCMOS has the same threshold as the 3.3V LVTTL, so  operation with 3.3-V TTL as well as 5-V TTL logic. 3.3-V CMOS and 5-V CMOS inputs are allowable with the SN75LVDS387.

Thanks

David

Hi David. I'm referring to 2.5V LVCMOS. My question is similar to this one. e2e.ti.com/.../2190098

Hi,

What is the VOH and VOL for the 2.5V LVCMOS you are using?

You need to make sure the SN75LVDS387 recommend operating condition of VIH 2.0 and VIL 0.8 are met by the VOH and VOL of the 2.5V LVCMOS.

Thanks

David

Hi,

I am afraid this device does not support 2.5 LVCMOS. V_IH and V_IL limits are not aligned with standard 2.5LVCMOS signaling levels.

For this FPGA,

VIH in range 1.8..3.3. VOH = 2.0
VIL in range -0.3..0.8. VOL = 0.4

Does TI offer anything else suitable? Thanks