• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 32 subscribers
  • Views 874 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ISO7420M failure to transmit data reliably

jon roadley-battin
Prodigy 70 points
Other Parts Discussed in Thread: ISO7240M, ISO7220M, ADS7886, ISO7240C

I am using the ISO7240M as a level shifter (5V -> 3v3) as well as an isolation chip

I am also using an ISO7220M  

These ISO chips provide isolation for four sADC chips (ADS7886) SPI data and control

The CLK is at 6MHz and this (and CS) passes over the dual ISO7220M as expected. However the returning data does not. When I compare the input and the output of the quad 7240M there is consistantly pulses being dropped (and in extreme cases a very short (more capacitive-shaped) pulse is seen (Which then isn't valid for the LVDS drivers). Looking at the bitstream it seems the lower 30% LSB are effected, this lines up with the fact when I am measuring DClink voltage (0->600V) the output is stepping in 50V steps while the sADC output has the resolution that is expected. I have replaced the quad a couple of times just incase it was damaged.

Rails on the primary (5V) and secondary (3v3) are very solid even when data transmission is occuring. There is plenty of decoupling (10uF tant 5mm away, 100nF and 10nF ~2mm away from pins) 

I am in the process of modding the card to remove the quad and use two dual's (since I know these reliably transmit the data). The quad is used on other cards in the project so I am more after any infomation as to any possible cause since this is going to have larger ramifications then just one card changing a 1x SOIC16 to 2xSOIC8 (this is before getting into sourcing and timescales)

  • 0
    Prodigy 70 points

    Modding in two ISO7220M has allowed the circuit to work 

    Pure speculation but:  From what I was seeing these ISO7240M were not infact M-grade (150Mbps) and fall over when hit with something that is 6MHz. order was for M, packaging was for M, IC label was M but the characteristics are not.

  • 0 in reply to jon roadley-battin
    TI__Mastermind 28265 points

    the ADS7886 has a 1MSPS max PSI interface. I suggest using the ISO7240C which come with internal noise filters.

    If using the M-version (which do not have internal noise filters) apply external RC filters (100 ohms, 100pF) at the isolator inputs.

    regards,

    Thomas

  • 0 in reply to Thomas Kugelstadt
    Prodigy 70 points

    Thankyou for the response. 

    I did concider the Cversion (and it was only lead-time from RS that stopped me trying it). 

    I am sorry but I cannot accept that this is simply a noise issue

     

    #1 if it was noise and the Mversion was susceptible to some noise in my application then why would two ISO7220M (modded in plus an additional ISO7220M) work where one ISO7240M would not. 

    Both are Mversions, both placed in pretty much the same location on the PCB (one of the duals shared some of the pads of the quad for easy modding). I would expect the 2x ISO7220M to actually be more noise susceptible due to the modwire and the additional distance to the decoupling caps, but that isn't the case I get out what I put in something I cannot say for the ISO7240M

     

    #2 Here are two scope plots.

    The 1st is primary side SCLK and SDO data 

    The 2nd is secondary side SCLK and SDO data 

    This was waveforms taken in-circuit while trying to measure 54Vdc. As you can see whole pulses are just missing.

     

    Reading: http://focus.ti.com/lit/an/slla284/slla284.pdf and refering to 1.2 LF-Channel Operation (since 150Mbps is used in relation to alot lower datarate) these ISO chips are not edge-triggered and thus if there was noise on the leading edge I would expect the ISO7240M to then aquire the data at the next internal OSC clock but as you can clearly see it isn't even transmitting the pulses. 

    I sorry but I am going to have to recomend such a chip is not used.

     

    I would also like to point out some errors in the datasheet. Max and typical are the wrong way round

    http://focus.ti.com/lit/ds/symlink/iso7220a.pdf

     

     

  • 0 in reply to jon roadley-battin
    TI__Mastermind 28265 points

    Jon,

    in regards to the data sheet "errrors", its not an error but an unlucky marketing aproach to show-case the isolators maximum speed. Basically the MAX column shows the  GUARANTEED maximum data rate, while the TYP column shows the typical possible maximum data rate. It is confusing and we plan to change this in future data sheets.

    With regards to the dual isolators versus the quad isolator design, they do have slightly different designs. We are going to investigate the quad isolators to see where this discrepancy might originate.

    Unfortunately at this moment I can only suggest to either sticking with the two dual isolators or moving your data rate away from the LF to HF transition range if using the quad isolator. I can fully understand your decision to not use the quad isolators at this type of frequency range.  

    I'll let you know of a work around solution as soon as we find one.

    Sorry for no better news at this moment.

    Regards, Thomas