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DS90UB953-Q1: Operating temperature issue of paired SER - DES at synchronous mode below -20°C

Part Number: DS90UB953-Q1
Other Parts Discussed in Thread: TIDA-01413, TPS65263, DS90UB960-Q1, DS90UB954-Q1, TPS650330, TEST

Hello team,

I discussed the issue of no link SER-DES below -30°C in recent time with Nick ...

Now we could isolate it: In Fail case there is a significantly increased oscillating of VDDPLL (pink curve - point 2; green - +1V8).

      

If we short circuit the ferrit bead at its ports the link establishes immediately and everthing is ok.

But it is a mystery to us, because this part of schematic has not been modified in our new design and layout.

Maybe an issue of the ferrit bead 742792662, but we couldn't confirm that.

The device selection seems to be ok and the bead has comparable features to the beads TI uses at its EVM kits.

By the way: In 953 data sheet there is a request for FB1-FB3: Z = 1 kOhm (@ 100 MHz) and RDC < 25 mOhm.

In several EVM kits the applied MURATA beads have up to 500mOhm RDC. Is the demand for <25mOhm to strong?

Regards,

Torsten

  • Torsten,

    Can you please share the full schematic here for review?

    Best Regards,

    Casey 

  • Hello Casey,

    how to share schematics as no public?

    Regards,

    Torsten 

  • Hi Torsten,

    I sent you a connection request so that you can share with me via private message.

    Regards,

    Nick

  • Hi Nick,

    last week I sent you our schematics via your private message.

    Did you receive it?

    Regards,

    Torsten

  • Hello Torsten,

    Please note that most of the team members for our group are out of office for the next two weeks or so due to the public holiday break so response times will be delayed during this time. Thank you for your patience in this and if you want to message me this schematic in the meantime I may have some time especially next week to help review that 

    Best Regards,

    Casey 

  • Hello Casey,

    I am conscious of the holidays at end of year and it is necessary for everybody. Nevertheless fine to read your message and offer and in the case of some time left ... Please let me know how to send a private message (schematics) to you. 

    Best Regards,

    Torsten 

  • Hello Torsten,

    I sent you a private message through E2E

    Best Regards,

    Casey 

  • Hello Casey,

    meanwhile (before XMAS) I sent you related schematics as private message - maybe you could find some time to check and to compare with our low temperature issue and oscillating voltage at VDDPLL.

    A related question:

    In case of down cooling of camera electronic from normal operation up to low temperature issue we observed the GENERAL_STATUS of SER 953 at register 0x52. It changed from 0x45 (normal operation) -> 0x47 (+ CRC error BC) -> 0x67 (+ Reserved(?)) -> 0x27 (no DES lock) -> 0x21 (no Forward Channel High Speed Lock) and sometimes to 0x20.

    What does 0x52[5] means? At present data sheet it is described as "Reserved", at an older one (June 10 2016) as "Bidirectional Control Channel Error Flag". Is this register value still valid and reliable? How to clear this bit, it does not change to zero even at normal operation.

    Regards,

    Torsten

  • Hello Torsten,

    In the schematic, the power supply decoupling for the 953 is not matching the requirements from the device datasheet which may be influencing some instability across operating conditions. The VDDPLL, VDDDRV, and VDDD pins should each have 1uF cap after the FB to GND in place of the current 100nF caps at each rail. Also pins 10, 15, and 26 should each have an extra 10nF cap to GND. 

    Also the PoC network is not matching our recommended network components so I would suggest to adjust that to match the network in the datasheet as it is finely tuned to meet the channel requirements of the serializer. 

    For 0x52[5] please ignore this bit. It is not expected to give any valid information about the link like the other non-reserved bits. 

    Best Regards,

    Casey 

  • Hello Casey,

    thanks a lot for your detailed check of our schematic.

    I agree with you concerning the differences at capacitances at power supply and at pin 10, 15 and 26. So I replaced and/or added all capacitors you mentioned in order to coincide exactly with SER data sheet. Concerning PoC network there are some slight differences, but we tried to adapt it to different modes (CSI-2 2G, 4G or compatibility), so it should work and it was designed according to 

    • DS90UB97x-Q1 FPD-Link IV Power-Over-Coax Design Guidelines and
    • DES-Hub-Board of TI (TIDA-01413).

    The repeated tests at temperature below -30°C led to no progress - we lost the SER-DES link after a short duration of operation. In order to exclude an impact of PoC network, we separated transmission (single ended FPD3 at coax)  and supply (12V) by removing L4, but there was no difference.

    The issue is a little bit strange, because there is a camera almost identical at our company working properely. We only changed the signal type from differential (STP) to single ended (coax) by adding a PoC network + signal termination and by the way we improved the PMIC by replacing TPS65263 by TPS65033007.

    The STP camera is reliably working below -40°C whereas the PoC one becomes instable below -30°C.

    What could be the reason for?

    Regards,

    Torsten   

  • Torsten,

    Can you have a look at the power supplies to the device to make sure that the DC levels and power supply ripple at low temp is meeting the datasheet spec? Also what are you connecting to on the other end? A TI deserializer EVM?

    Best Regards,

    Casey 

  • Hello Casey,

    thanks for your information.

    At DES side we usually apply an own design with 960 (and PoC-Adapter if applicable). I made the tests once more with DS90UB954-QEVM at the other end. We measured  the power supply voltages in parallel at the corrected PoC cam.

    May be ripple of VDDD leads to the issue at low temperature, whereas +1V8 is completely stable (though all SER voltages are derived from). Our former STP cam with almost equivalent design has no ripple but differs at PMIC (TPS65263 vs. TPS 65033007).

    Where does the VDDD ripple comes from?

    Best regards,

    Torsten

  • Hey Torsten,

    Yes it does look like you are getting relatively significant ripple at low temp with the new design and that seems like to be contributing to your issue. I would suggest to focus on reducing that ripple - maybe there is something that can be fixed in the PS design but that part TPS65033007 is covered by a different team within TI. I will transfer your ticket to a different group who may be able to help further with that part. 

    Best Regards,

    Casey 

  • Hello Casey,

    We have assigned this ticket to the appropriate engineer and they will be getting in touch with you in the next day or so.

    Regards,

    Alex

  • Hi Torsten,

    I can help regarding the TPS65033007 PMIC in your investigation. Can you please accept my E2E friend request and send over the relevant schematics for review? I would also like to see how VDDD, VDDPLL, and VDDDRV are connected relative to +1V8 since this rail appears to be stable in all scenarios. 

    Additionally, are these waveforms measured on the serializer or deserializer supply?

    TPS65033007 is a camera module PMIC (serializer side), but the image titles say "at DS90UB954-Q1" or "at DS90UB960-Q1", which are deserializers. 

    Thanks,

    Gerard

  • Hi Gerard,

    thanks for your offer for support.

    First of all I accepted E2E friends.

    It is correct that +1V8 is stable and all other voltages are derived from that with each a ferrit bead (WE742792662) similar to the Murata ones in TI EVMs (BLM18AG102SN1). I measured all voltages at PoC camera board nearby SER 953. 

    Camera (as you can see in schematics I sent as a private message) consists of Imager, serializer, power supply (PMIC) and some stuff. For transmission of data the other, receiving end was of interest and that was either DES DS90UB954 or DES DS90UB960 -  but there were always the same issue. In order to find an explanation, why +1V8 is stable and behind the beads there is such a significant ripple: The ripple has a harmonic frequency of around  130kHz. 

    Evaluating the resistance it leads to around or more than 4Ω at this frequency and a current oscillation could cause uch a ripple, may be?

    Best regards,

    Torsten

  • Hello Casey,

    thanks meanwhile I was contacted by Gerard from other team.

    There is still a question: 

    The STP cam (picture right) with same beads etc. has no ripple at all. The PoC cam has already low level ripple at operation. The most significant different of both cams is that one has a termination to GND (single ended) and the other not. Where does the current oscillation with around 150kHz come from? At 150kHz the bead has a resistance of around 4Ω?

    Best regards,

    Torsten 

  • Hi Torsten,

    High Q output filters could result in oscillation depending on the filter cutoff frequency and the preceding regulator's control loop characteristics. I see your scope shot states "Cs added / replaced according to 953 datasheet".

    1. Does this include adding 1 uF at each of the VDDPLL, VDDDRV, and VDDD pins?
    2. Have you tried the same measurement replacing the WE bead with the recommended Murata bead? 

    Thanks,

    Gerard

  • Hi Gerard,

    to 1: Yes.

    to 2: We intend to do this, Muratas are ordered. Nevertheless these WE beads should have better parameters and at our similar camera with TPS65263 and SER 953 but with differential output the electronic works without oscillations at VDDD, VVDDDRV and VDDPLL.

    Regards,

    Torsten   

  • Hello Casey,

    do you have an idea where the approx. 150kHz oscillation could come from?

    Best regards,

    Torsten

  • Hello Torsten,

    Just to let you know Gerard is out of office today but should be back tomorrow to address your concerns. Thank you.

    Regards,

    Alex

  • Hi Torsten,

    If there was an issue with the PMIC I would expect to see some oscillation on the +1V8 rail. Since this rail is stable in the above scope shots, the oscillation may be the result of some interaction between the ferrite bead filter and the serializer supply pins. 

    From what I can see the WE beads have a higher inductance and smaller resistance, which could increase the filter Q factor enough to make the design marginal. The TPS65263 may have mitigated these effects with its different control scheme (current mode with external compensation) compared to the TPS650330 (voltage mode with internal compensation). 

    Please let us know how the testing goes with the Murata beads and we'll continue troubleshooting if the issue persists. 

    Thanks,

    Gerard

  • Hi Gerard, 

    thanks - this explanation could be a real approach of issue, because a replacement of bead by a resistor with 2,2 suppressed the oscillation in a sufficient amount. I let you know the results with Murata asap.

    Regards,

    Torsten

  • Hi Torsten,

    That's great to hear - please feel free to post again here or start a new thread once you've completed your testing.

    Thanks,

    Gerard

  • Hi Gerard,

    I think, you gave the decisive hint and explanation. The change of PMIC to the TPS650330 with different control (voltage mode with internal compensation) and the high Q factor of WE bead led to the oscillation of VDDPLL especially and hence link disruption. We repeated the tests with Murata bead of EVM (BLM18AG102SN1D - but larger  package) and a more suitable bead of WE with lower Q factor (WE 782 631 111). The results of both tests (temp step test -40°C ... 85°C) provided a PASS.

    Thanks a lot once more

    Torsten