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DP83620: Strapping for SD_TIME bit in SD_CNFG

Part Number: DP83620

Hello

We are trying to configure DP83620 tor EtherCAT Network and one of the requirements is to enable FAST LINK LOSS detection.

DP83620 documentation stated fast link loss can be enabled by setting SD_TIME control in the SD_CNFG register.

It is possible to set SD_TIME by doing the strapping instead of explicit register write

Thank you

Alan