In the 954 datasheet the Power Up Sequencing figures 55 and 56 show a hard reset after the first PDB. Is this a requirement, recommendation, or only there to show if you do a hard reset after power up the required timing(t7 and T8)?
If VDD18, VDDIO, and REFCLK are all stable before PDB goes high, is the hard reset still required/recommended?
Thanks,
Justin
