DP83TG720R-Q1: Go in Sleep Mode

Hello Viktor Gerlach

Thank you for the query.

Does the  DP83TG720R-Q1 enter the Sleep Mode ?

Please refer to Figure 7-12. Required Implementation for Sleep Mode

Regards,

Sreenivasa

Hello Kallikuppa Sreenivasa-

Thank you for your quick reply.

In the State Diagram is described Power-off -> Reset PHY Disabled

It is possible? Power off -> Sleep Mode when only VSLEEP Power is provided and the other Power rails not.

Best regard

Viktor Gerlach

Hello Viktor Gerlach

Thank you for the reply.

Could you please complete the below sentence.

It is possible? Power off -> Sleep Mode when only VSLEEP Power is provided and the other Power rails not.

Regards,

Sreenivasa

Hello Kallikuppa Sreenivasa-

Thank you for the reply.

My question is: Enter the PHY automatic the Sleep mode when only VSLEEP Power is provided and the other Power rails not?

We wanted to use it to enable our main Power supply.

Best regards

Viktor Gerlach

Hello Viktor Gerlach

Thank you for the reply.

Enter the PHY automatic the Sleep mode when only VSLEEP Power is provided and the other Power rails not?

I reworded the question. You ware looking to understand the below 

Will the PHY enter the sleep mode automatically when only VSLEEP Power is provided and the other Power rails are disconnected (not)? 

Regards,

Sreenivasa

Hello Kallikuppa Sreenivasa-

Thank you for the reply.

Yes, this is the question:

Will the PHY enter the sleep mode automatically when only VSLEEP Power is provided and the other Power rails are disconnected ? 

Best regards

Viktor Gerlach

Hello Viktor Gerlach

Thank you for the reply. 

Let me check and comeback to you in a couple of days.

Regards,

Sreenivasa

Hello Viktor Gerlach

Please refer to below sections in the datasheet.

7.4.5 and 7.4.6

Regards,

Sreenivasa

Hello Viktor Gerlach

Please refer below for additional details on the sleep mode implementation.

Will the PHY enter the sleep mode automatically when only VSLEEP Power is provided and the other Power rails are disconnected ? 

The device will be in a mode similar to the sleep mode when all the power supplies are cutoff.
However, INH will be still high. This will take extra current of VSLEEP/R, R is approximately equal to pull down resistance on INH.

In his case INH is unusable for connecting to PMIC.

A register write will be required to pull the INH low during sleep mode as below 
Local sleep entry for Master mode phy :
• Step 1 : Write bit[7] = 'b1 of register[0x018B].
• Step 2 : Make "wake" pin low and hold it low for sleep mode.

These register settings will make the phy transition to sleep mode. We can then cutoff the power supplies.

Regard,

Sreenivasa

Hello Viktor Gerlach

Please expect delay in response due to year end holidays.

Regard,

Sreenivasa

Hello Kallikuppa Sreenivasa-

Thank you for the reply.

I wish you a happy New Year.

You wrote: In his case INH is unusable for connecting to PMIC.

What is the minimum voltage for INH?

Best regards

Viktor Gerlach

Hello Viktor Gerlach,

Thank you for the reply. Wish you a happy new year2022.

You wrote: In his case INH is unusable for connecting to PMIC.

This is without the register write. Here is the INH behaviour from the datasheet

INH: Active-HIGH PMOS open-drain output. When the PHY enters the sleep state, PHY will release the INH pin
to allow an external pull-down resistor (recommended value = 10 kΩ) to pull the line to ground. When in any other
state, the INH pin will drive a HIGH state to the VSLEEP rail.

What is the minimum voltage for INH?

Could you please elaborate the above question.

Regards,

Sreenivasa