Hi team,
One of our customers has the following problems.
Dear TI FAE:
I will elaborate on the problems I encountered here, please solve them or give suggestions, thank you.
Brief description of the project: Desktop cash register dual-screen display, CPU is MediaTek MT8365 (i350), because the main screen occupies the platform mipi interface, so the secondary screen display implementation solution is CPU dpi (rgb 8bit dual edge) to dsi mipi (used by the conversion IC It is lontium LT9211_U5, placed on the motherboard side), but due to the structure ID limitation, the motherboard is far from the secondary screen interface (about 300mm), so TI SN65DPHY440SS is added to the secondary screen small board to enhance RX EQ and adjust HS data The rise and fall timing of /clk are used to adjust the mipi effect and enhance the transmission distance.
Remarks:
1. The cable uses a twisted pair (170mm), and the FPC and PCB are matched with 100Ω±10% impedance；
2. As the ESD problem was solved before, I2C mode is now adopted.
Encountered problems:
test signal integrity mipi eyes fail, the frequently reported fail items in the following report, please help explain and give suggestions for modification, the attachment will upload the corresponding test report and specification, please check it.
Our test instrument uses Keysight MSOS804A Mixed signal Oscilloscope" (8 GHZ 20GSa/s 10-bit ADC), D9020DPHC MIPI D-PHY Test (version: 3.73.1.0), CTS version: V1.0, continue clk.
1) 1.3.11{HS Data TX 20%-80% Rise Time (tR)} ,1.3.12{HS Data TX 80%-20% Fall Time (tF)} reports an error failure, can I modify the 0X0B of TI-SN65DPY Register to improve, please refer to the test report to give the modified value of the register.
2) 1.4.9 {HS Clock TX Common-Level Variations Between 50-450MHz(VCMTX(LF))}, 1.4.4 {HS Clock TX Differential Voltage(VOD0 Pulse)}, 1.4.4{HS Clock TX Differential Voltage( VOD1Pulse)}, 1.4.5 {HS Clock TX Differential Voltage Mismatch (Pulse)} error fail, whether these four items can be improved by modifying the 0X0E register of TI-SN65dphy, please refer to the test report to give the modified value of the register.
3) 1.4.11{HS Clock TX 20%-80% Rise Time (tR)}, 1.4.12{HS Clock TX 80%-20% Fall Time (tF)} reports an error failure, can I modify the 0X0A of TI-SN65DPY Register to improve, please refer to the test report to give the modified value of the register.
4) 1.5.4 {Data to Clock Skew(TSKEW(TX))(Max,Min), 1.5.4{Data to-Clock Skew(TSKEW(TX))(Mean)}, what do these two items reflect? Whether there will be any improvement after adjusting the rate of HS data/clk, please refer to the test report and give suggestions for modification.
Please pay attention to the above questions and give feedback in time, thank you!
8176.MIPI D-PHY Device 1_Report_2021-12-16_1126软件修改花屏+线束包铜箔.pdf
4035.LT9211_Datasheet_R2.5.pdf
Best Regards,
Amy Luo
