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SN75DP159: inquire about lane & polarity swap function

Part Number: SN75DP159

Hi TI experts,

Customer plan to design SN75DP159 to improve HDMI signal condition.

But there is problem that TMDS signal pattern is crossed. please see the attached file.

Inquire_SN75DP159 20220107-1.pptx

1page : this page is ideal condition.

2page : customer design condition(Crossed pattern).

3~4page : As a result, the customer wants to configure in-out as shown in 3-4.

5page : We checked the comment in datasheet that output line cannot be changed.

Question1 :  is it right? Can't we configure output lane like 3-4?

Question2 : I need your advice on PCB pattern design when TMDS signal is crossed. Please tell me your idea.

Question3 : Please see the page7 in PPT. This is a question about the DEV_FUNC_MODE function. customer video spec is 4k, 60hz. They thought that HDMI signal quality would be better if set to Automatic Retimer for HDMI 2.0. However, the quality was better when set the automatic driver to timer crossover at 1.0 Gbps in the actual test. Please answer the customer's question.

"We would like to ask TI to confirm whether there are any other customers asking the same opinion as ours and whether this IC function is correct."

Thank you.

Downey Kim.

  • Downey

    For question 1 and 2, the DP159 has fixed outputs, OUT_CLK(pines 25 and 26) will always send the HDMI clock required for synchronization, this output has to be connected to TMDS_CLK. But you can change the order of data lanes as long as the lane order matches between the input and the output.

    For question 3, can they read the TMDS_CLK_RATIO_STATUS? Are they seeing this bit being set to 1 when in HDMI2.0 operation?

    Thanks
    David