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DS90LV028A: LVDS Signal

Carlo
Expert 7715 points
Part Number: DS90LV028A
Other Parts Discussed in Thread: TS3USB221

Hello team,

Is there a problem if LVDS signals are applied to the device without the device being powered?

Regards,
Carlo

  • 0
    TI__Guru 64326 points

    Hi Carlo,

    This device has a fail-safe feature for the powered down while terminated condition. See section 8.3.1 Fail-Safe Feature in the datasheet. 

  • 0 in reply to Malik Barton57
    TI__Expert 7715 points

    Hello Malik,

    If the device is powered down, how can its output be high?

    Regards,
    Carlo

  • 0 in reply to Carlo
    TI__Expert 7715 points

    Hello Malik,

    Any update on this? Thanks.

    Regards,
    Carlo

  • 0 in reply to Carlo
    TI__Guru 64326 points

    Hi Carlo,

    Sorry I miss understood your question. It is my understanding that if DS90LV028 is powered off there should not be LVDS signals at it input. 

  • 0
    Prodigy 10 points

    Hi Malik,

    Thank you for your support so far. Carlo directed me here to discuss a follow-up topic with you.

    In our design, the LVDS signals are generated by an FPGA which is powered independently from the circuit containing the receiver. The receiving circuit is supposed to turn on shortly after the FPGA. Therefore, the 1.2 V common mode voltage is present on the LVDS lines before the receiver is up. In the current prototype this does not cause any isssues but we wanted to make sure that this is safe. As it appears not to be within the specification of the receiver, do you see any solution other than making sure that the FPGA is not powered until the DS90LV028 is powered?

    Thank you, Jelle

  • 0 in reply to Jelle Dijkstra
    TI__Guru 64326 points

    Hi Jelle,

    It is good to know that there is no functional issue here however it is hard to saw what effect this could cause over time or various parts. Another solution here could be a simple mux can be used to connect the LVDS lines when DS90LV028A is powered. TS3USB221 is an example. Powering up the FPGA can work as well but may not be feasible.