Dear support,
My customer need to optimize drastically the power consumption of our retimer (in coef x3/board).
Could you help on the following points:
- From datasheet, maximum power consumption is during CDR locking phase. Do you have information regarding mean CDR locking time when a signal is present ?
- What is affecting CDR locking time in the signal provided ? Bit pattern ?
- Static power consumption is 325mW typical but 1325mW maximum, what could cause the retimer to go to maximum static power consumption ?
- Is there a way to reduce channel power consumption other than deactivating DFE if not needed (but that’s only 25mW saved) ?
- We would have two “main” cases of maximum power consumption
- First is with DAC passive cables, there are not drawing power, so in this case we could allow retimer to consume 5-6W (each)
- Second is with QSFP+ optics module, that will consume between 1 and 2W each. In this case we need to reduce retimer power consumption to around 3W (each), but track length to/from QSFP+ module would be short (~6 cm) so we could deactivate DFE, reduce VOD, and maybe have other tricks ?
- We would have two “main” cases of maximum power consumption
- What’s the influence of VOD and edge rate on power consumption ? Do you have a power estimator ?
- Regarding layout and power supply, it seems that the retimer has a good internal power filtering. Is it possible to use only one DC/DC to provide 2.5V to the 3 retimers, or should we use 3 independent DC/DC to avoid power supply noise between chips ?