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DS125DF1610: Power consumption optimization

Part Number: DS125DF1610

Dear support,

My customer need to optimize drastically the power consumption of our retimer (in coef x3/board).

Could you help on the following points:

  1. From datasheet, maximum power consumption is during CDR locking phase. Do you have information regarding mean CDR locking time when a signal is present ?
    1. What is affecting CDR locking time in the signal provided ? Bit pattern ?
  2. Static power consumption is 325mW typical but 1325mW maximum, what could cause the retimer to go to maximum static power consumption ?
  3. Is there a way to reduce channel power consumption other than deactivating DFE if not needed (but that’s only 25mW saved) ?
    1. We would have two “main” cases of maximum power consumption
      1. First is with DAC passive cables, there are not drawing power, so in this case we could allow retimer to consume 5-6W (each)
      2. Second is with QSFP+ optics module, that will consume between 1 and 2W each. In this case we need to reduce retimer power consumption to around 3W (each), but track length to/from QSFP+ module would be short (~6 cm) so we could deactivate DFE, reduce VOD, and maybe have other tricks ?
  4. What’s the influence of VOD and edge rate on power consumption ? Do you have a power estimator ?
  5. Regarding layout and power supply, it seems that the retimer has a good internal power filtering. Is it possible to use only one DC/DC to provide 2.5V to the 3 retimers, or should we use 3 independent DC/DC to avoid power supply noise between chips ?
    1. From datasheet, maximum power consumption is during CDR locking phase. Do you have information regarding mean CDR locking time when a signal is present. What is affecting CDR locking time in the signal provided ? Bit pattern ?
      • The CDR locking power consumption refers to the short 100ms period while the retimer is acquiring CDR lock. After lock is acquired power consumption settles to the "CDR locked" value
      • This power consumption will have negligible variation with bit pattern
      • We typically recommend that the "CDR locking" power consumption only be used for system voltage regulator selection. For system thermal simulations the CDR locked power consumption parameter should be used
    2. Static power consumption is 325mW typical but 1325mW maximum, what could cause the retimer to go to maximum static power consumption ?
      • This is purely based on variation across device process voltage and temperature
    3. Is there a way to reduce channel power consumption other than deactivating DFE if not needed (but that’s only 25mW saved) ?
      • Unfortunately there is not. The CDR functional blocks + EQ dominate the power consumption, and these blocks need to be enabled for normal operation
    4. What’s the influence of VOD and edge rate on power consumption ? Do you have a power estimator ?
      • It's negligible. it would probably be within ~5mW
    5. Regarding layout and power supply, it seems that the retimer has a good internal power filtering. Is it possible to use only one DC/DC to provide 2.5V to the 3 retimers, or should we use 3 independent DC/DC to avoid power supply noise between chips ?
      • That should be feasible. The key is to make sure the regulator can provide sufficient current for all retimer even if all retimers are attempting to acquire CDR lock simultaneously.
      • You would also want to check the power supply noise level to ensure it is within the recommended guidelines per the TI datasheet

    Thanks,

    Rodrigo Natal