DP83TG720S-Q1: voltage requirement when external crystal is used

Part Number: DP83TG720S-Q1

hello their, 

customer is working on external crystal design for dp83tg720s-Q1.

however, on the datasheet, I don't find the voltage requirement for XI pin.

would you please share the voltage requirements of dp83tg720s-Q1's XI pin, like the image shown below.

BRs,

Shubiao Wang

  • Hi Shubiao,

    It is recommended that the oscillator or the clock buffer feeding XI to be run on VDDIO so that the signal level to be fed to XI is also at VDDIO level.

    --
    Regards,
    Gokul.

  • Hello Gokul, 

    what about the requirements for external crystal?

    BRs,

    Shubiao

  • Hello Shubiao,

    Can you please let me know what do you mean by external crystal?

    Does it mean the external crystal feeding to the external oscillator?
    In this case, the crystal specifications should be dictated by the external oscillator vendor. We need to ensure that the the output of the oscillator (the clock feeding to XI) need to meet '25 MHz OSCILLATOR REQUIREMENTS' mentioned in the datasheet.

    --
    Regards,
    Gokul.

  • As you said, clock for oscillator feeding XI should be reach up to VDDIO level.

    But what if clock from external crystal?

    In datasheet for crystal requirement, Frequency, Frequency tolerance and ESR specification are given, but the amplitude is not mentioned. Is that mean the amplitude of clock feeding XI could be any level, such as 0.1Vpp or below? Wheather 1Vpp is OK?

  • Hi Chen,

    Crystal is a passive element and doesn't need any active power supply. We can't control the level of XI the crystal feeds to the device. The Crystal and the crystal oscillator circuit inside the device interact with each other to get sufficient amplitude of level for the circuit to oscillate at 25MHz.

    Please let me know if you need more details.

    --
    Regards,
    Gokul.

  • Thanks.

    ESR of crystal in datasheet is required 50Ω below, if I place a crystal with ESR of 60Ω, would be OK?

  • Hi Chen,

    The ESR higher than 50ohms will impact the power-up timing and might violate the device internal power-up constraints.

    Higher ESR also affects the EMI/C immunity margins and hence not recommend.

    --
    Regards,
    Gokul.

  • Do you mean that ESR impact the Crystal stabilization-time post power-up(T5.3 in datasheet)? Would you share the exact relationship between ESR and power-up delay? T5.3 has be shown the typical value, what is the maximum? 

    If power-up timing is not good, will the phy work noramlly after making a hardware reset when power and clock of crystal keep on?

  • Hi Chen,

    Crystal and the crystal oscillator inside the PHY interact with each other generate 25MHz clock. If the ESR of the crystal is higher, the oscillator circuit takes more time to settle and can violate some internal power-up timing constraint.

    If the crystal stabilization is not met, hardware reset most likely will make the PHY work. But if the ESR is not met, the stabilization time exponentially increases depending on the margins of the design and it is difficult to quantify the maximum stabilization time. Without the maximum stabilization time, we can never know when to apply hardware reset.

    --
    Regards,
    Gokul.