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TNETE2201B: REFCLK Jitter Spec and Generation

Francisco Tejada
Prodigy 20 points
Part Number: TNETE2201B
We are trying to interface to the TNETE2201B with an FPGA that is being driven by a crystal reference. The jitter requirement on REFCLK is very tight at 40ps, though, and we are concerned that the FPGA could add jitter to the REFCLK/transmit data before being sent to the TNETE.
Have any other users successfully used a REFCLK that is passed through an FPGA or similar logic block?  Does the REFCLK for the TNETE2201B need to come directly from a crystal source to meet this specification?
Currently we are sending the transmit data (K28.5 D5.6 idle sequence) and REFCLK from the FPGA and we are experiencing some trouble getting the TNETE to lock. We have tried enabling/disabling REFCLKEN and neither have been able to reliably lock onto our IDLE data stream.
  • 0
    TI__Mastermind 24282 points

    Hi Francisco,

    I don't see this part implemented too frequently, so unfortunately I am not able to comment on "Have any other users successfully used a REFCLK that is passed through an FPGA or similar logic block?" from experience.  With that said, I would expect that as long as the FPGA clock output meets the jitter requirement, than the clock shouldn't be the issue.

    Are you able to lock to the IDLE data stream at all?

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    Prodigy 20 points

    Thank you for your response and help.  We are not able to lock onto the IDLE stream.  We are monitoring the input and output data on a logic analyzer.  At times it seems the output is locked to the input data but no SYNC signals are produced by the part.  We are using the following bits for the IDLE data

    001111 1010  101001 0110
    Can you confirm if this is the correct sequence?  This sequence is not balanced, we are not sure if that matters to the TNETE.  We are also not sure if the TNETE only recognizes the negative K28.5 character for SYNC or if it also recognizes the positive K28.5 character.
    Thank you
    Francisco
  • 0 in reply to Francisco Tejada
    TI__Mastermind 24282 points

    Hi Francisco,

    I'm looking into this and can follow up with more details tomorrow.

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    TI__Mastermind 24282 points

    Hi Francisco,

    Thanks for your patience.  I have several questions regarding your system.

    • Do you know if your REFCLK meets the jitter requirements?
    • Have you tried transmitting data with this part?  If so, have you been successful?

    It also seems like it would be important to have a DC balanced pattern.

    Thanks,

    Drew