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# DS90UB925Q-Q1: PCLK jitter tolerance

Part Number: DS90UB925Q-Q1

Hi Team,

We meet flicker issue when using 925-926, and see lock lost when flicking. We'd like to check the jitter at 925 PCLK input side.

Here comes some questions:

1. Jitter tolerance:

1) In datasheet, minimum tolerance is 0.4UI, but no max jitter requirement. Is it jitter tolerance (jitter < max jitter tolerance) or eye opening (eye opening > min eye opening)?

2) If PCLK is 30MHz, 0.4UI is 0.4*1/30M = 13.3ns, right? I asked because in datasheet, the note says 1UI = 1 / (35*PCLK)

2. Test method:

In TI CTP document, it's based on DPOJET jitter analysis software, is there any guideline to use Infinite mode to measure jitter? Should we read the jitter of 3rd clock cycle?

Regards,

Cera

• Hi Cera,

1) In datasheet, minimum tolerance is 0.4UI, but no max jitter requirement. Is it jitter tolerance (jitter < max jitter tolerance) or eye opening (eye opening > min eye opening)?

Min spec is the min our device can tolerate. In other words, 0.4 UI of jitter is the guaranteed minimum that the device will tolerate. Less is better.

2) If PCLK is 30MHz, 0.4UI is 0.4*1/30M = 13.3ns, right? I asked because in datasheet, the note says 1UI = 1 / (35*PCLK)

That's not the correct way of calculating it. You forgot to include the 35 bits of data that the forward channel is composed of.
The UI is the UI of the FPD channel, not the PCLK signal. Because the PCLK is used to drive the forward channel signal
That being said, the following is the correct calculations:

• PCLK = 30 MHZ, 1UI=1/(35*30MHz)=0.95ns
• 0.4UI=0.38ns (Min for tIJIT)
In TI CTP document, it's based on DPOJET jitter analysis software, is there any guideline to use Infinite mode to measure jitter? Should we read the jitter of 3rd clock cycle?

That's not the right method. You need to use a proper jitter analysis software that allows you to do a Clock recovery (CDR) emulation with specific bandwidths to match our device – Software such as DPOJET or equivalent to characterize that. Keysight or other vendors have similar jitter analysis SW

Regards,

Thanks for your timely help. I still have a question about UI.

The UI is the UI of the FPD channel, not the PCLK signal. Because the PCLK is used to drive the forward channel signal

In my understanding, UI is the cycle time of a clock. When I monitor PCLK jitter, I think the 1UI of PCLK is 1/PCLK. 1UI of FPD-Link data should be 1/(35*PCLK). Is that right?

If PCLK jitter is calculated using FPD-Link data rate, the PCLK is too strict. It's 0.4*1/35 of the PCLK period.

Regards,

Cera

• Hi Cera,

Yes, UI is based on FPD-Link frequency which is calculated as 35*PCLK.

Input jitter tolerance is defined here from FPD rate and corresponding PLL allowance on DES side. So PCLK jitter might be okay for video input, but not okay after the 35x multiplier in the devices PLL.

Regards,

Logan