Hi,
I'm successfully using a DP83822 in FX mode for optical communication to a "PHY" implemented in a FPGA. Now I'd like to utilize the BIST mode of the DP83822, in which it generates frames containing pseudo random sequence, to check for errors at the other end. I've been able to make the PHY emit such frames even in FX mode, but yet wasn't able to correlate the bits received in FPGA with any PRBS generation method.
Are there any details known about the PRBS generation and how the generated bits are packed into the frame? I can see J/K symbol and Ethernet preamble, followed by somewhat random bits.. But how are they generated? Using the common x^15 + x^14 + 1 PRBS15? Is there any bit/byte/nibble-reordering in effect? What methods can be used to synchronize to the pattern in a receiver?
Lower byte of register 0x1B according to documentation is 0x7D "equal to 500 bytes" (ie. effectively multiplied by 4?).
The packet length specified in register 0x1C doesn't exactly correspond to the actual number of symbols x 2 on line. There seems to be some overhead in addition to the Ethernet preamble, maybe synchronization info?
I'd appreciate if someone could help me with more details.
Thanks in advance!
Kolja