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DP83848J: DP83848J-PHY Configuration Issue

Jaya Shree C P
Prodigy 40 points
Part Number: DP83848J
Other Parts Discussed in Thread: DP83848C

Hi, 

I am using an Altera Cyclone III and trying to communicate with DP83848JSQ from an FPGA.

Even I did not plug the RJ45 jack of Altera Cyclone III to PC, the link up status always high. I have tried reading BMSR register. Here am getting 0x883a.

Do we have any specific configuration to initiate PHY?.

In my code, I have configured some control register bits. Those are below.

phy_cfg

{

BMCR                    0x8000 (for self -clear)

ANAR                    0x01E0

BMCR                    0x1200

}

I have a register configuration profile for DP83848C & 78Q2120C (attached below), similar like do we have for DP83848J?

Ex: PHY Name    : National DP83848C

PHY OUI    : 0x080017

PHY Model Num. : 0x09

PHY Rev. Num. : 0x00

Status Register: 0x00

Speed Bit   : 0

Duplex Bit   : 0

Link Bit    : 0

 

"Teridian 78Q2120C",

            0x39C,              // OUI

            0x0C,               // Vender Model Number

            0x9,                // Model Revision Number

            1,                  // Location of Status Reg

            14,                 // Location of Speed Status

            13,                 // Location of DuplexStatus

            2,                  // Location of Link Status

            &teridian_phy_cfg,  // Function pointer to

            &teridian_link_status_read

And also question about the PHY TX_CLK and RX_CLK:

We have two boards, one has Teridian PHY IC another has TI PHY IC(DP83848J), I am able to get clock frequency from TX_CLK and RX_CLK pin on Teridian IC, but we didn't get signals when tested on TI IC(DP83848J). Please provide your comments.

  • 0
    TI__Genius 17740 points

    Hi Jaya,

    By writing the value 0x01E0 to register 0x4, you are erasing the protocol selector bit[1] for IEEE802.3. Please change this value to 0x01E1, and re-run your config function.

    There is no specific configuration to initiate the PHY. 

    What do you mean by "the link up status always high". A BMSR reading of 0x883a shows bit 2 is 0. 

    Thanks,

    David 

  • 0 in reply to David Creger
    Prodigy 40 points

    Hi David,

    Thanks for your quick response.

    We have modified suggested register value and tested it on db83848j but there is no improvement.

    What do you mean by "the link up status always high". A BMSR reading of 0x883a shows bit 2 is 0. 

    For the above one, I am telling about network status always in live State even I did not plug the RJ45 jack of Altera Cyclone III to PC.

    And also quick question about the PHY TX_CLK and RX_CLK:

    We have two boards, one has Teridian PHY IC another has TI PHY IC(DP83848J), I am able to get clock frequency from TX_CLK and RX_CLK pin on Teridian IC, but we didn't get signals when tested on TI IC(DP83848J). Please provide your comments.

     Thanks,

    Jaya Shree C P

  • 0 in reply to Jaya Shree C P
    TI__Genius 17740 points

    Hi Jaya,

    In regards to the link status always being high, the PHY register 0x0001 bit[2] shows the link status according to the PHY, so I am not able to help with a link status other than that.

    Which MAC mode is the device being placed into?

    Thanks,

    David