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DP83822I: TX problem in large packets (PCS loopback)

Part Number: DP83822I

I have a DP83822IRHBR PHY connected to a XC7Z020 (ZYNQ), RGMII mode, 10Mbps. The receive path works fine, no problems getting data. When transmitting I can only transmit packets up to about 128 bytes then I get RX errors. I put the part in PCS loopback and attached the scope capture, why am I losing lock?

PHY register dump:
   Reg: 0x0000    Data: 0x0100
   Reg: 0x0001    Data: 0x784d
   Reg: 0x0002    Data: 0x2000
   Reg: 0x0003    Data: 0xa240
   Reg: 0x0004    Data: 0x01e1
   Reg: 0x0005    Data: 0x0000
   Reg: 0x0006    Data: 0x0004
   Reg: 0x0007    Data: 0x2001
   Reg: 0x0008    Data: 0x0000
   Reg: 0x0009    Data: 0x0000
   Reg: 0x000a    Data: 0x0100
   Reg: 0x000b    Data: 0x1000
   Reg: 0x000c    Data: 0x0000
   Reg: 0x000d    Data: 0x0000
   Reg: 0x000e    Data: 0x0000
   Reg: 0x000f    Data: 0x0000
   Reg: 0x0010    Data: 0x4007
   Reg: 0x0011    Data: 0x0108
   Reg: 0x0012    Data: 0x2000
   Reg: 0x0013    Data: 0x0800
   Reg: 0x0014    Data: 0x0000
   Reg: 0x0015    Data: 0x0000
   Reg: 0x0016    Data: 0x0101
   Reg: 0x0017    Data: 0x1249
   Reg: 0x0018    Data: 0x0480
   Reg: 0x0019    Data: 0x8021
   Reg: 0x001a    Data: 0x0000
   Reg: 0x001b    Data: 0x007d
   Reg: 0x001c    Data: 0x05ee
   Reg: 0x001d    Data: 0x0000
   Reg: 0x001e    Data: 0x0002
   Reg: 0x001f    Data: 0x0000
   Reg: 0x0461    Data: 0x0410
   Reg: 0x0462    Data: 0x0000
   Reg: 0x0463    Data: 0x0000
   Reg: 0x0464    Data: 0x0000
   Reg: 0x0465    Data: 0xff00
   Reg: 0x0466    Data: 0xff00
   Reg: 0x0467    Data: 0x0fc3
   Reg: 0x0468    Data: 0x0000

  • Hi Wade,

    The packet size dependency may hint at a buffer under/overflow issue. Can you measure the RX_CLK and TX_CLK frequencies, and ensure these signals meet the specifications listed in section 7.16 of the datasheet. Send me a scope shot if possible.

    Thanks,

    David

  • David, thanks for the reply. This is exactly what I did today. I had an issue on the ZYNQ correctly setting the GEM_CLK. The clock was running at 2.6MHz in 10Mbps mode, not good for clock recovery. I was able to fix this in the ZYNQ side.