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[FAQ] How can I ensure a successful PCIe Gen5 design?

3 Tips for a successful PCIe Gen5 design

With PCIe datarates increasing to 32Gbps in the latest PCIe Gen5 specification, PCIe has allowed for data higher throughput than ever before.  Unfortunately, higher data rates can also mean more signal integrity issues.  Failure to account for signal degradation in the design phase can significantly affect the performance of the completed system and add time to your design cycle.   They say an ounce of prevention is worth a pound of cure, and that cannot be more true when it comes to a high-speed design.   Following the best practices below will help ensure that your next design is successful in the first iteration.

1) Simulate your design with an IBIS-AMI model

  • IBIS-AMI models are files used in simulation software to describe the performance of I/O buffers or differential lines for a given IC.  This format is designed specifically with high-speed signal integrity in mind, and obtaining one is the first step in ensuring that the board design performs well.
  • Many of our high-speed signal conditioning products have a IBIS-AMI model that can help verify the performance of a given IC in a board design.  In order to request the IBIS-AMI model for a given product, click on the "Request Info" button on the product page.
  • When performing the simulation, it is important that the input data pattern matches the real-life data pattern as closely as possible. Different input patterns can result in different simulation results.
  • Run the simulation using an S-Parameter model that matches the actual media that will be used.  In order to obtain accurate simulation results, an SnP file should be extracted from the actual media that will be used in the application. 
  • Connectors can also contribute to signal degradation, specifically in the form of crosstalk.  Using an SnP file that closely represents the connector being used will also increase the accuracy of the simulation.
  • When evaluating the results of the simulation, use eye masks defined by the PCIe specification.  Meeting this criteria will ensure that the electrical characteristics of the system are PCIe compliant.

2) Optimize the PCB layout

  • An IBIS-AMI simulation may reveal weaknesses in the PCB design.  In order to correct for these issues, it is important to optimize the PCB board layout for high-speed signaling. 
  • An ideal high-speed PCB design should have low loss traces, optimized return loss, and minimized cross talk.  In order to achieve this, close attention should be paid to the layout of the PCB board.  Below are some of the more common issues present in poor PCB design:
    1. Impedance changes - When a high-speed signal is traveling through a channel, impedance discontinuities can cause reflections of the signal back towards the source.  Impedance changes can be caused by passive components, solder joints, vias, and more.  It's best to avoid them completely, but when that is not possible, care should be taken to minimize changes in impedance in order to reduce reflection and signal degradation. 
    2. Connector or Via Stubs - An extreme example of an impedance discontinuity is an open section of channel created by a through-hole via or connector.  These stubs will completely reflect a signal and can cause resonance at certain frequencies.  To correct for this, vias should be back-drilled to prevent reflections from stubs.
    3. Inconsistent ground reference - Ensure there is a ground reference throughout the length of the high-speed channel.  This includes adding ground vias next to any signal vias in the path, and ensuring that there is a solid, unbroken ground plane under signal.
  • High-speed design is a subject that has been extensively studied and requires specialized knowledge.  Luckily, TI has created some guides to help you through the high-speed layout design process.  Refer to our PCIe Layout Guidelines for more information about optimizing the PCB layout.
  • Finally, if possible, use a 3D High-Frequency Structure Simulator (HFSS) in order to identify any remaining issues and refine your design before fabricating.

3) Perform Interoperability Testing

After board has been fabricated, the electrical characteristics of the design will (hopefully) be well within PCIe specifications.  However, this is not where testing ends.   Interoperability testing is an important step to ensure that the digital portion of the design can work well in any PCIe system.  However, it is often difficult or expensive to test with the many PCIe devices that exist in the market.  Especially in the case of PCIe Gen5 where there are a limited number of devices that are publicly available to test with.  One way to get the resources you need is by attending a PCI-SIG workshop.  At the PCI-SIG workshop, your system or add-in card will be tested with the multiple different PCIe vendors.  Not only will this confirm that your product works well with others, it will also test many other aspects of your design to ensure that it is fully PCIe compliant, and give your product the best chance to succeed in the market.