SN65DSI84: register configuration with DSI-Tuner

Glenn,

Could you tell me how exactly I can compute the correct DSI CLK frequency from the 1.5 Gbps per lane value?

The correct DSI CLK frequency calculation does not include 1.5 Gbps directly in the calculation. Additionally, the four DSI data lanes per channel operating up to 1 Gbps per lane not 1.5.

See below to calculate. From the datasheet you gave LVDSCLK = 54MHz.

Step 8:

Fill out the CLK inputs. The LVDS CLK frequency should be given in the timing table in the display datasheet (refer to step 3). For this display it is 70.6 MHz.

You can use either the DSI CLK input or an external reference clock to source the LVDS CLK. This example uses the DSI CLK to source the LVDS CLK.

To determine the DSI CLK frequency, use the following equation:

Thanks,

Zach

Glenn,

It sounds like you have the correct understanding. If you run into anymore issues feel free to start up another thread.

If you have no other questions, please click the  "this resolved my issue" button.

Thanks,

Zach