If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

P82B96: Interface forum

Part Number: P82B96

Dear suport team.

I am trying to understand the explanation of "10.2.1.2 Detailed Design Procedure" in the datasheet while calculating with the help of the annotations of figures 7-figure 9.
However, I cannot understand the formulas written in the annotations of figure 7 to 9. Please help me.

First, about the formula of figure 7 "Effective Delay of SCL at Slave"
What does the first term 255 represent? I looked in the datasheet, but the constant 255 only appears here.
What does the constant 17 in 17VCCM mean?
What does the constant 2.5 in parentheses mean? Its mean the RX/RY input capacitance of 2.5pF (typ)? If so, why isn't 2.5 multiplied by 10^-12?
Why multiplying Cb by 4x10^9? What does 4x10^-9 mean?

Next, about the formula of figure8 "Effective delay of SCL at master"
What does 0.7 in 0.7RbCb mean? It seems that the value is different from the input "High" threshold (0.58xVCC).

Finally, about the formula "Effective delay of SDA at master" in figure 9
What does 0.2 in 0.2RsCs mean?

Thank you and regards,

• Hello,

I will respond by noon 10/24/2022.

Regards,

Tyler

• Hi again,

What does the first term 255 represent? I looked in the datasheet, but the constant 255 only appears here.
Why multiplying Cb by 4x10^9? What does 4x10^-9 mean?
Why multiplying Cb by 4x10^9? What does 4x10^-9 mean?

These constants seem to be built into the equation based off the device architecture and the setup. I am not finding anything in the datasheet that references these numbers.

For the 255, I was thinking it had to do with an I2C message being sent. 1ns / bit for ~32byte message sequence, but I am probably wrong here.

A better reference for the number 255 might be the buffer delay time on falling input listed in 7.9 in the switching characteristics in the datasheet, since the number 270ns shows up in the second equation in figure 8.

The 4x10^9 seems to be seems to be an arbitrary number for the clock stretch period based on pg. 17 of the datasheet.

What does 0.7 in 0.7RbCb mean? It seems that the value is different from the input "High" threshold (0.58xVCC).

The 0.7 represents worst-case bus rise time (0-70%) of RbCb. Instead of using the I2C spec rise time of 30-70%, we use a wider range for some headroom.

What does 0.2 in 0.2RsCs mean?

This seems to be another built in constant based on the architecture of the device.

I might be able to find more information about these constants. It might be sometime before I can dig up that data.

Regards,

Tyler

• Hi Tyler

The task I was given by a customer is to provide an indication of the allowable capacitance for cables when using relatively short cables (less than 10m).
I found understanding the "10.2.1.2 Detailed Design Procedure" very helpful for this task. And I calculated the 25m cable example myself to try to get a better understanding.
However, even if I apply the values ​​in Table 1 to the equations in figures 7 to 9, I could not get 490ns for SCL delay and 570ns for SDA delay.
So, I also suspected that calculating the delay might require special calculations related to the device architecture, so I posted the question.

From your answer, it seems to be very difficult for you to find the meaning of the constants and coefficients that I asked last time.

1. Calculation process of "the falling edge of SCL is delayed 490 ns".
I have a feeling that the sum of the following values ​​will roughly match 490ns.
· Falling delay value calculated from the output impedance of the TX/TY terminal estimated from the VOL characteristics and the cable capacitance.
· Propagation delay of each part
I want to check if it is correct, so please show me a model of the calculation process.
2. Calculation process of " the SDA rising edge is delayed 570 ns."
3. Why define "the clock is stretched 400 ns".
From the context of "10.2.1.2", I think that since the required Low period is 635ns short of the standard 1300ns, it should be simply written to program Low period=1935ns. (clock stretch=635ns)

Best regards,
Masaki

• Hi Masaki,

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/870398/p82b96-how-to-calculate-the-bus-delay?tisearch=e2e-sitesearch&keymatch=P82B96%252525252520calculation#

I think this helps to explain roughly where these delays come from.

Regards,

Tyler

• Hi Tyler,

Thanks for pointing me to a post that might be helpful.

Unfortunately, Bobby's post doesn't seem to fully answer my question.
Regarding 400ns, Bobby's answered that it depends on the architecture of the device, but there seems to be no confirmation.
Also, regarding the 490ns calculation, he says that the 45ns calculation does not fit.
I suspect that Bobby made a mistake in applying the delay values ​​from the "7.9 Switching Characteristics" table.
Since the load conditions in TEST CONDITION in the table in section 7.9 and the load conditions in figure 10 and Table 1 are different, I thought that there was a difference in the transient response time.
Therefore, subtracting the values ​​in notes (1) to (4) in the table in section 7.9 from the delay values ​​in the table, and calculating the transient response time again, I got a total of about 485ns.
However, when the calculation of 570ns is done with the same idea, the total exceeds 800ns!
Something is wrong with my idea too.
From the above, I think that the delay values ​​in the table in Section 7.9 include the transient response time due to the load, but since it is difficult to separate it, I will simply consider the worst value of the device propagation delay.
And I will add the transient response time due to the load.
I think that the delay margin will be too large, but I think we can avoid the situation where the system does not work.
Do you have any suggestions for this?

The datasheet for the P82B96 is very difficult to understand because the calculation assumptions are sorely omitted.

Please tell me one more thing. The P82B96 is also sold by NXP and the datasheet is very similar, but where was it originally developed?

Best regards,
Masaki

• Hi Masaki,

I think that all of us are trying to figure out information that potentially is meant to be kept as constants in the datasheet. I suspect that those values are listed as is because of the way the chip is internally designed. Adding explanation to those constants to explain where they result from is probably divulging too much information on the way TI fabs these devices. I think we can guess and get close, but otherwise I am unable to help find an exact reason for some of these numbers in the datasheet.

NPX P82B96 is similar to TI P82B96. Based off when the datasheets were released, it looks like NXP was released first.

Regards,

Tyler