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DP83867CS: DP83867CS

Part Number: DP83867CS

I see this question has been asked many different ways but looking for best recommendation for connecting two PHYs (DP83867's) board to board across a backplane (just a few inches)?  I could go transformerless, 1 transformer or 2 transformers since board space is not an issue.

Which is best for 1000BASE (1GbE) operation.

1) transformerless (capacitive coupled)

2) 1 transformer (single transformer between the PHYs center tap with decoupling cap on each side)

3) 2 transformers (2 transformers back to back with center tap decoupling cap on phy side, 50ohm termination in between)


  • Hi Don,

    Option 3: 2 Transformer as described in datasheet Section Cable Line Driver would be the best solution.

    If you wanted to use Option 1; the 869 would be a better choice.



  • Hi Alvaro,

    Thanks for the response but I have another question.  We are designing a system using a SMARC processor module that has the DP83867 on board without any transformer.  The destination for the 1GbE is another custom module plugged into the same carrier and need SGMII at that interface - see attached block diagram.  Do I need 2 transformers and on the carrier PWA?  The distance between them will be <1".  Also we're stuck with the 867 on the SMARC module but can use any PHY on our carrier card.



  • Hi Don,

    Please allow me some more time to get into contact with someone in my team to answer this. If I cannot reach them today, I will back to you after Thanksgiving Holiday, on Monday Nov 28th. Apologies for the potential delay.



  • Hi Don,

    What is the connection interface between the SMARC Module to the 867?

    I believe 2 transformers is necessary for this application with the 867.

    However, with the 869 you wouldn't need them at all, connect the SMARC Module(RGMII) -> 869 (SGMII) -> FPGA



  • The SMARC (and ComExpress) module contains an Intel Atom uP as well as the 867 PHY onboard connected via RGMII.  Unfortunately the RGMII is not routed out of the SMARC module, just PHY level ethernet (GBE0_MD0± to GBE0_MD3±).  So seems I need to translate PHY level signals.  I was trying to avoid the 1 or 2 transformers but if they are needed then will add them.