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TCA9548A: I2C switch doubt

Part Number: TCA9548A

Hi TI Guru,

I plan to use TCA9548A in my design however i have some doubt here, and my use case as below.

Master side (1.8V pull up), Slave side (3.3V pull up), VCC = 1.8V (Vpass about 1V from figure 14)

1. How the device do the translation since it is a passive switch, once the gate is on, master and slave will be connected. Hence, in my used case, the I2C line will be 3.3V once the gate is ON ?

2. Total capacitance for TCA9548A when all gate is on, Total Cap = 28+8*7.5 = 88pF, am i get it right?  (I just need the calculation for TCA9548A only, i will add master and slave devices in my calculation)

3. Is the Pull up resistance calculation is parallel all the pull up resistor? ex. Master 10K, all Slave 10K, is it equivalent to pull up of 10K/9 ?  

Thanks in advance

Best regards,
Alder

  • 1. The gate voltage is 1.8 V. So for voltages above riughly 1 V, the switch is open, and the voltage at the other channels is determined by the pull-up resistors.

    2. Those capacitance values are specified only for when the switch is off, so you do not see all channels. The datasheet does not specify the on capacitance.

    3. The pull-up resistors of all enabled channels act in parallel.

  • Hi Alder,

    (1) Since VCC = 1.8V, gate voltage of internal passFET is biased to 1.8V. Any signal below 1V will begin to turn on the passFET, pass a LOW signal from main I2C bus to the selected channels. Above 1V, internal passFET becomes HIGH-Z. 

    (2) Clemens' is correct here. Datasheet only specifies off capacitance for each channel. On-capacitance would be slightly different. Also, this calculation is dependent on how many channels you desire to have active at once. Worst case of course would be the way you are attempting to calculate it, since this device can have all channels active at once.

    My suggestion would be to adhere to rise-fall time specifications of the I2C standard during testing. You can also use off-capacitance as an estimate. 

    (3) I agree with Clemens. Pull-up resistors will act in parallel for all active channels. 

    Regards,

    Tyler

  • Thanks Clemens and Tyler.

    1. I am thinking why the switch open, i just see the PU voltage. Please see picture below. When the channel 0 selected (which is 3.3V PU), i see 3.3V at master side ?

    2. Can you help to provide on-capacitance for the device? i might in the case that all 8 channels is turn on, thus i need to do calculation.

    As i will provide my board to other party which they do not have rework capabilities, hence i need to set it right at the first time.

    3. Noted on the PU and thanks,

    Best regards,
    Alder

  • 1. I am thinking why the switch open, i just see the PU voltage. Please see picture below. When the channel 0 selected (which is 3.3V PU), i see 3.3V at master side ?

    1.8V. The FET between the two sides is in the cut-off region of operation. Vgate is ~1.8V on the FET. The 1.8V main SDA/SCL pin which I will refer to as the source is also 1.8V due to the pull up resistor. Vgate-to-source < Vth therefore cut-off region or simply high impedance.

    2. Can you help to provide on-capacitance for the device? i might in the case that all 8 channels is turn on, thus i need to do calculation.

    I talked with a designer who told me that on-capacitance is tricky to measure in real life. In the design environment he stated the on capacitance was expected to be similar to the off capacitance. I would suggest you use the same number provided in the datasheet.

    -Bobby