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DP83826EVM: A Layout Question of surge voltage protection on RJ45 Differential Pair Routing

Yuanchen Zhu
Intellectual 380 points
Part Number: DP83826EVM

Dear TI Expert,

  We have a quite detailed layout quesiton which concerns us on the aspect of EMC surge test. In the pcb design file of DP83826EVM, we can see the routing of signal trace on the top layer and PGND copper pour on the second layer for RJ45 section, as below:

Top Layer

                 

Second or Other Layer

The through mount RJ45 connector would make differential signal quite close to second and other layer PGND via the through hole, as shown in the screenshot.

If there's a high surge voltage, say 1 or 2kV for EMC surge test coupling into the ethernet cable, the spacing or clearance seems not enough, which may break down and damage the clearance and make signal line conduct to PGND for good.

Correct me if I am wrong, e.g. according to IPC-2221, the clearance calulated for 1kV (DC or AC) should be 1.5mm or so for internal layer, which is far larger than the spacing as we see now. 

How should we consider this? Do we miss or misunderstand anything? Would appreciate any advice or suggestion.

Regards,

Yuanchen Zhu

  • 0
    TI__Mastermind 21556 points

    Hi Yuanchen,

    Let me check with the team on this. Due to the Holidays, I will get back to you next week.

    Thanks,

    David

  • 0 in reply to David Creger
    TI__Mastermind 21556 points

    Hi Yuanchen,

    I am not aware of the standard you are referencing. The EVM was not optimized for EMC performance, and is intended for functional evaluation only. So you are correct, further optimizations of the board should be made for EMC testing.

    Thanks,

    David

  • 0 in reply to David Creger
    Intellectual 380 points

    Hello, David

      I see. Do we have any reference layout design of ethernet RJ45 port, which has been optimized for EMC consideration, so that we can refer to follow? Thanks.

    Yuanchen Zhu

  • 0 in reply to Yuanchen Zhu
    TI__Mastermind 21556 points

    Hi Yuanchen,

    Attached is a board that was used for EMC testing with DP83826. You can reference the RJ45 layout here. 

    Adapter board_DP82836_GCD.zip

    Thanks,

    David

  • 0 in reply to David Creger
    Intellectual 380 points

    Still, I am confused. As we can see in your second screenshot, the PGND copper pour on second layer is still quite close to differential signal through hole. Does that mean that spacing is of enough isolation for surge test between signal path and PGND?  How do we consider the spacing?  If there's anything not clear here, please point out. Thanks.

    Yuanchen

  • 0 in reply to Yuanchen Zhu
    TI__Mastermind 21556 points

    Hi Yuanchen,

    I am not aware of the rule you are referencing. Can you share the relevant section from the IPC standard?

    Thanks,

    David

  • 0 in reply to David Creger
    Intellectual 380 points

    “ The chart is adapted from columns B1, B2, B4 of IPC 2221B Table 6-1. It lists recommended minimum spacing between internal and external conductors as a function of peak working voltage level for intended use at altitude below 3050 meter (10.007 feet).” 

    Since your team is not aware of this fact, I am just curious that have the adapter board DP82836 passed IEC61000-4-5 surge test for ethernet port and to which level (1kV or 2kV)?

    My purpose to post this question is to double check anything I may miss which make us able to leave this small spacing and pass surge test at the same time.

    I understand the PGND underneath signal path would make good characteristic impedance, and would like to finely control to leave as least discontinuity as possible. Any more advice or suggestion?

    Thanks.

    Yuanchen

  • 0 in reply to Yuanchen Zhu
    TI__Genius 16030 points

    Hello Yuanchen,

    With the layout shared by David earlier, we passed 1KV (class B) as per IEC61000-4-5 Surge test.

    Yes we recommend continous ground under the routes for good control of impedance. You may isolate the connector ground from board ground. At least keep a foot print to put a few 0ohm resistors and capacitors( to tune the capacitor reistor values if desired during EMC tests).

    --

    Regards,

    Vikram

  • 0 in reply to Yuanchen Zhu
    TI__Mastermind 21556 points

    Hi Yuanchen,

    Yes, the board I shared has passed IEC61000-4-5 surge testing to +/-2kV. 

    The note you shared recommends 1.5mm as the "peak working voltage level". I think this is the disconnect, then, since this spec is assuming constant voltage for extended periods of time, but ESD strikes are very brief so there may be no issue. Would you agree?

    Thanks,

    David

      

  • 0 in reply to David Creger
    Intellectual 380 points

    Hi, David

     Okay. In the case that 1.5mm is only necessary for "peak working voltage level", then one last question: Is there any specified minimum clearance on pcb , for internal layer and outer layer respectively, required for taking care of surge test @ +/- 2kV in the similar scenario, recommended by TI ?

    In other words, in the current case, can we take that 10mil is enough for IEC61000-4-5 +/- 2kV in internal layer according to TI?

    Thanks.

    Yuanchen

  • +1 in reply to Yuanchen Zhu
    TI__Mastermind 21556 points

    Hi Yuanchen,

    You can take that 10mil is enough for IEC61000-4-5 +/- 2kV in internal layer, yes.

    Thanks,

    David