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TIOL1113: How does the a fault voltage affect the chip the voltage level on the LDO

Jan Bock
Intellectual 2830 points
Part Number: TIOL1113

Hi Team, 

can you help with the question below:

currently we are in the development of an IO-Link product again at the safety consideration.
We would use the TIOL1113.
The question is, if the 60V is present at pin L+ or CQ in the event of a fault, what happens to the communication ports and the LDO output?
What voltage levels can be expected here?
We would expect these to stay in the specified range. Is this the case?
I would be very happy to receive feedback in a timely manner.

Thanks

Jan

  • 0
    TI__Mastermind 26776 points

    Jan,

    Yes, since the absolute maximum rating of L+ and CQ is ±60 V (or transiently ±65 V), the logic pins and power supply would stay within their specified ranges. When operating outside of the recommended operating conditions for the device, you will see parametric shift or communication interruption, but the device should not sustain damage. Thus, overvoltage at the logic or supply output pins would not be expected.

    Best,

    Danny

  • +1 in reply to Danny Bacic
    TI__Mastermind 28850 points

    Jan,

    To add to what Danny said, the high abs max voltage level is for transients and not DC operation.  In the event of a fault condition where the L+ or CQ pins are shorted to 60V, the current flowing through the device will increase the power dissipation and result in the device entering a thermal shutdown condition and the CQ driver will be disabled.  The LDO will remain on, but there will be no communication through the transceiver as a result of the disabled driver and fault condition.

    The TIOL1113 device is designed to check every 15ms to see if the fault condition has cleared.  Once it is cleared, the device will resume normal operation.

    Regards,

    Jonathan

  • 0 in reply to Jonathan Nerger
    TI__Intellectual 2830 points

    Hi Jonathan, Hi Danny, 

    thanks for the answers. What is about the  RX, TX, EN, WAKE und NFAULT Pin. Is there any risk for the microcontroller when a fault event occurs?

    Thanks 
    Jan

  • +1 in reply to Jan Bock
    TI__Mastermind 28850 points

    Hi Jan,

    All of these pins operate of the LDO side of the device and will remain at the LDO voltage level (3.3V for the TIOL1113).  The LDO will dissipate more power as it steps the 60V fault down to 3.3V, which will increase the device temperature and possibly trigger a thermal shutdown event.  But the 60V will not pass through to the logic pins and pose a risk to the microcontroller.

    Regards,

    Jonathan