We're using a DP83822H in our design that's configured for MII. The XI pin is getting 25 MHz. The problem we have is that when setting for 10 Mbps operation, we are seeing 1.25 MHz at the RX_CLK and TX_CLK outputs (we should be getting 2.5 MHz). When trying to run at 100 Mbps operation, we are seeing 12.5 MHz at the RX_CLK and TX_CLK outputs (we should be getting 25 MHz). Looks like there is an extra clock division happening here. Any ideas on why this is happening? Are there some specific configuration settings that might be causing this?
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