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TCAN4550-Q1: GPIO1 & GPO2 (TX & RX Mode)

Part Number: TCAN4550-Q1
Other Parts Discussed in Thread: ISOW1044, TCAN4550

Hi Team,

We would like to ask you help regarding our customer's inquiry below.

Current we have a client Product that having 4 of TCAN4550RGYRQ1 on same Board and each connected to CAN Isolator ISOW1044 Via pins GPIO1 & GPO 

Client request to tie all 4 controller to 1 Isolator via (GPIO1 & GPO) Pins 

Kindly advice if this configuration is valid for both  TCAN4550RGYRQ1 &  ISOW1044

Regards,

Danilo

  • Hi Danilo,

    I'm not sure I understand the desired use case here. The GPIO pins of TCAN4550 operate as the TXD and RXD signals for CAN when the device is In controller test mode. Because each TCAN4550 will be driving its own TXD signal, tying these pins together would result in contention. A block diagram of the intended solution may be helpful for my understanding.

    Is the intention that the four separate CAN ports would all be connected to The same CAN bus? Or do they intend to save on isolator cost by reducing the number of ISO ICs that they need?

    Regards, 
    Eric Schott 

  • Hi danio

    Thanks a lot for reminder email i actually did miss other email for some reason  

    Hi Eric, 

    Sorry for late reply really appreicate your support

    Actuallly i had same impression would TCAN4550 work properly via GPIO and GPO and did ask about it though i got feedback that is OK 

    so it is really a good chance to validate this point since i can't judge 

    Regarding main question yes using 4x  TCAN4550  with on  1x ISOW1044 

    Block diagram in this link below 

    https://ibb.co/52SrQ3J

  • Hi Amr,

    Our internal firewall is blocking the link you shared. Would it be possible to share the block diagram as an image directly in your post? You can use the "insert" tool to attach an image to your reply.

    Alternatively, you can share the document with me directly via email. You can find my contact information by clicking on my E2E name.

    Regards, 
    Eric Schott 

  • Hi Eric, 

        Yes i used insert and found attach by link , on second check found it could be directly uploaded kindly find below 

  • Hi Amr,

    Thanks for sharing the diagram directly. 

    The solution that has all of the GPIO2 pins of the TCAN4550s tied together is not advisable. These output pins are push/pull and will contend when trying to drive their unique CAN data. These signals could be ANDed together with open-drain-like translators in order to derive a single TXD signal for the transceiver without risking contention with the controller digital pins. Keep in mind that this will introduce further propagation delay in the network that will need to be accounted for when determining the maximum possible arbitration rate. 

    Regards,
    Eric Schott

  • Hi Eric 

    really appreciate your reply and recommendation. regarding that my mistake sorry i named GPO2 as GPIO2 sorry about that from datasheet this pin is Open drain already as stated below

    8.3.13 GPO2 Pin

    GPO2 pin is an open drain configurable output function pin that provides selected interrupts. This pin needs an external pull-up resistor to VIO to function properly. The output function can be changed by using register
    16'h0800[23:22] and can be configured as a watchdog output reset pin.
    In test mode, this pin becomes the RXD_INT_PHY transceiver output or TXD_INT_CAN CAN Controller output pin

  • Hi Amr,

    Very perceptive here. However, I believe that this pin is not an open drain when it is configured for use in test mode. In order for the TXD pin of a CAN controller (or RXD pin of a CAN transceiver) to effectively drive the speeds that are required for 5Mbps CAN FD communication, this pin needs to operate in a push-pull mode so that there is good symmetry between rising and falling edges and the transition time is well controlled. Because of this, the GPO2 pin will switch to its drive mode for this configuration. 

    These are some of the limitations that the above system will face if all of these TXD signals are combined using open-drain logic. 

    I realize this is not explicitly stated in the datasheet at the moment. The closest I can offer is what is shown in Figure 8-2 below. We are working on a document that will explain how to use test mode in more detail. In parallel, I will see if we can revise the datasheet to reflect this behavior. 

    Regards,
    Eric Schott