HI TEAM
I want to ask if there is a problem with my current design?
Please see the attachment
UBIQCONN_HDMI Level Shift Hybrid redrive_ted0604i_20230314_01.pdf
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HI TEAM
I want to ask if there is a problem with my current design?
Please see the attachment
UBIQCONN_HDMI Level Shift Hybrid redrive_ted0604i_20230314_01.pdf
Hi,
Please see attached for my review comment and let me know if you have any questions.
UBIQCONN_HDMI Level Shift Hybrid redrive_ted0604i_20230314_01_TI_Reviewed_03172023.pdf
Thanks
David
Hi,
Also, is the source a DP++ source? The schematic has the net name of DVI, so I want to make sure if the source is a DP++ AC coupled or DVI DC coupled source.
Thanks
David
Hi David
The GPU is INTEL Coffee Lake Refresh- H CPU, and the output is DVI/HDMI signal.
Thanks
Hi,
If the Intel Coffee Lake Refresh-H CPU output is DVI/HDMI, then you want to replace the TDP0604 input capacitors with 0-ohm resistor since DVI/HDMI is a DC-coupled interface.
Thanks
David
HI David
Modify the schematic for the input capacitor with a 0 ohm resistor.
please see Attachment...
UBIQCONN_HDMI Level Shift Hybrid redrive_ted0604i_20230322_01.pdf
question:
Regarding the setting of the pull-up/pull-down resistor of TDP0604, is my current definition correct?
Hi,
You can reference to this app note for the TDP0604 configuration, https://www.ti.com/lit/an/slla589/slla589.pdf.
1. For DDC buffer, you need to have the 1.8k pullup on the HV_DDC_SDA/SCL as shown below
2. Tie CFG0 and CFG1 to ground through 1k resistors
3. EQ0/1 need to be tuned depending on the compliance test result.
Thanks
David