Hi Team,
We have T1024 processor with DP83867IR PHY in our design.
PHY is operating in 3 supply mode.
And PHY power on sequence is as below.
1.0v(VDD1P0) -> 1.8V(VDDA1P8) -> 2.5V(VDD2P5,VDDIO)
It worked good for 3 years, but the datasheet says that
the 1.8-V VDDA1P8 supply must be stable within 0- 25 ms of the 2.5-V VDDA2P5 supply ramping up.
did we make a mistake?
We can not change the dcdc sequence in our design now.
So what will happen to the DP83867 PHY device?
Does it cause malfunction or damage to the DP83867 PHY device?
thanks and regards