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DS90UH941AS-Q1: 941

Part Number: DS90UH941AS-Q1
Other Parts Discussed in Thread: DS90UB941AS-Q1, CDCEL913, CDCE913

Ds90ub941as q1 is a deserializer. I use 913 as the reference clock for 941 here. I only need to configure the value of the 0x56 register as 0x01. Do I need to configure any other registers.I am using the splitter mode. When 913 outputs 184mhz to 941, one screen has vertical stripes and the other screen is black.

  • Hi,

    DS90UB941AS-Q1 is actually a serializer, not a deserializer. You cannot connect two serializers together so I'm not sure how you are seeing anything on a screen. You can refer to the datasheets to see a list of compatible serializers and deserializers.

    Best,

    Lucas

  • HI Lucas,

    When I use the 192mhz clock frequency divided by 8155, the screen can display stably.

    When using the 192mhz clock frequency given by cdcel913, it was found that there was a slight jitter in the frequency and a jagged pattern around the image.

    From the oscilloscope, it can be seen that the frequency of the REFCLK pin of 941 is also unstable.

    I used the 941 splitter mode, do I need to configure the 941 register when using the 913 clock frequency. Now only the 0x56 register of 941 is configured.

    Thank you for your support

    Regards,

    Huizhou

  • Hi Lucas,

    I am the FAE supporting Pateo. For the above problems, I hope you can help to find out whether it is caused by the jitter of the clock, and whether the customer needs to conduct further tests to help confirm. Looking forward to your guidance.

    Thanks!

  • Hi Huizhou and Alan,

    Can you send me a block diagram explaining your system design? Both 941 and 913 are serializers which cannot be connected together, so I don't understand how your system is working or how you're able to see something on the display.

    Best,

    Lucas

  • HI Lucas,

    913 refers to the cdcel913 clock chip.

    Project as shown in the picture

  • Huizhou,

    Can you provide the full programmed settings for 941AS? What are you configuring for the  SPLIT_CLK_CTL registers? 

    For support specifically on CDCE913 I would recommend creating a separate thread. If the clock frequency is moving around, then this is definitely not supported with 941AS so that would be a separate problem - I can't tell from your video if that is real or a measurement error. Also it doesn't seem like jitter - more like massive frequency deviation 

    -Casey