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DP83TG720R-Q1: DP83TG720R-Q1

zhang qijun
Prodigy 10 points
Part Number: DP83TG720R-Q1

In DP83TG720R-Q1 datasheet， it has defined the below reset Timing:

    

we have below questions：

a) Does the VDD contain all the power supplies of VDDA VDDIO VDD1P0 in the figure?

b) VDDA VDDIO VDD1P0 power supply which module of Phy IC? If VDDA and VDDIO come up first, VDD1P0 comes up later, or MCU reset causing VDD1P0 voltage be lowered and then raised, which will have an impact on the establishment of Ethernet communication?

c) What is the specific function of Bootstrap Latch-in? Does it control by STRIP_1 Pin (14th Pin of the Phy IC)?

d) If DP83TG720 first initialization fails， does the Phy chip can support retry initialization again? if yes, how to config it when retry it again?

e) During the power up Timing, Does the Hardware Reset_ N Pin also need to be config By MCU SW in the same way as Reset Timing?

  • 0
    TI__Expert 8435 points

    Hi Zhang,

    zhang qijun said:
    a) Does the VDD contain all the power supplies of VDDA VDDIO VDD1P0 in the figure?

    Yes

    zhang qijun said:
    b) VDDA VDDIO VDD1P0 power supply which module of Phy IC? If VDDA and VDDIO come up first, VDD1P0 comes up later, or MCU reset causing VDD1P0 voltage be lowered and then raised, which will have an impact on the establishment of Ethernet communication?

    As long as you follow the requirements in section 7.6 Timing Requirements, they can come up in any order. Please note the PHY will not work unless all rails are powered up.

    zhang qijun said:
    c) What is the specific function of Bootstrap Latch-in? Does it control by STRIP_1 Pin (14th Pin of the Phy IC)?

    The bootstrap latch in asserts what bootstraps the PHY is set to.  STRP_1 is used for strapping the phy address (PHY_AD), it is one of pins used to adjust the bootstrap mode

    You learn more about bootstraps by reading section 8.5.1 Strap Configuration in the datasheet or watching this video on bootstrapping: https://www.ti.com/video/series/ti-precision-labs-ethernet.html

    zhang qijun said:
    d) If DP83TG720 first initialization fails， does the Phy chip can support retry initialization again? if yes, how to config it when retry it again?

    What do you mean by a failed initialization? A failed initialization indicates there is some issue in the system, it should not happen with our PHY.

    zhang qijun said:
    e) During the power up Timing, Does the Hardware Reset_ N Pin also need to be config By MCU SW in the same way as Reset Timing?

    RESET should be HIGH during power up.

    Best regards,

    Melissa