TDP0604: EQ Gain Adjustment for CLK Lane

Phil OConnor

Part Number: TDP0604

Hello,

I have a TDP0604 in a DP tp DP linear redriver configuration set over I2C. I am trying to tune the EQ settings for my losses on board via I2C registers. The register sets have explicit 0-15 bit for EQ settings on lanes D0-D2. Which registers affect and can set the EQ settings of the CLK lane?

Thanks.

over 1 year ago

+1 David (ASIC) Liu over 1 year ago

TI__Guru**** 161866 points

Hi,

You can use register 0x13 to program the clock lane EQ. The bit mapping of the register 0x13 is the same as the bit mapping of the data lanes.

Thanks

David

+1 Phil OConnor over 1 year ago in reply to David (ASIC) Liu

Prodigy 20 points

Hey David,

The fix is not verified yet but this should solve my problem. Register 0x13 is not shown in the TDP06041 data sheet and is missed - consider updating this at some point. Thank you very much.

Interface

Interface forum

TDP0604: EQ Gain Adjustment for CLK Lane