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DS90UB941AS-Q1: split mode support – Left/Right setting questions

Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: ALP, USB2ANY

Hi team:

I used the 941AS splitter mode but could not output the picture. Besides, I try config SA8155 output 1920x720 or 960x720 size image ,and config ub941 work in single FPD-LINK Transmitter mode, Panel0 can display image

More Info:

1. Host SoC: Qcom SA8155

2. Host Soc output timing info:

1920*720@60

    uVisWidth        = '1920'
    uHsyncFrontPorch = '50'
    uHsyncWidth      = '50'
    uHsyncBackPorch  = '50'
    uVisHeight       = '720'
    uVsyncFrontPorch = '50'
    uVsyncWidth      = '50'
    uVsyncBackPorch  = '50'
    uPixelFreqInHz   = '108054000'
960*720@60
    uVisWidth        = '960'
    uHsyncFrontPorch = '25'
    uHsyncWidth      = '25'
    uHsyncBackPorch  = '25'
    uVisHeight       = '720'
    uVsyncFrontPorch = '50'
    uVsyncWidth      = '50'
    uVsyncBackPorch  = '50'
    uPixelFreqInHz   = '54027000'
3. config SA8155 output 1920x720 or 960x720 size image ,and config ub941 work in single FPD-LINK Transmitter mode, Panel0 can display image
4. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0xc,Panel0 can display image
5. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0x8,Panel0 can not display image
6. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0x8; 0x5b = 0x1,Panel0 can display image
Could you please help to check when i would like to use Symmetric Splitting - left/right setting, what configuration should be set to 941AS to successfully output the SoC picture? 
Thanks!
  • Hey Alex,

    I will review your request and get back to you within 1-2 business days. 

    Regards,
    Fadi A.

  • Hi Fadi

    Thank you very much.

  • Hey Alex,

    I need more information about your system configuration. If you are running 2 displays with resolution of 1920x720 with a superframe of 3840x720 then you can use the left/right splitting method explained in the datasheet (8.4.4.1 Left/Right 3D Format Support)

    A few things we need to know is your DSI source config:

    DSI Continuous Clock Mode:

    • Discontinuous DSI clock mode
    • Continuous DSI clock mode

    DSI input mode:

    • Dual-DSI mode
    • Single-DSI mode

    DSI PORT:

    • DSI Input port0
    • DSI Input port1

    DSI number of LANES:

    • 1 lane , 2 lanes, 3 lanes, 4 lanes

    I attached a script for 1920x720 with PCLK = 108 per display and Superframe 3840x720 with PCLK 216 Mhz and symmetric split application with 941AS for reference.

    3840x720 Sym Split Script Superframe_PCLK216.py
    # 3840x720@60 Symmetric Split Example - 2x 1920x720@60
    
    # Video 0 and Video 1 Parameters:
    # HACT = 1920
    # VACT = 720
    # PCLK = 108 MHz 
    
    # DSI Superframe Dimensions:
    # HACT = 3840
    # VACT = 720
    # PCLK = 216 MHz 
    
    # DSI clock = 648MHz
    # DSI Lane Speed = 1296Mbps/lane 
    # 4 Lanes DSI
    # DSI input port 0
    
    import time
    
    UB941AS = 0x18
    
    board.WriteI2C(UB941AS,0x01,0x02) # Reset
    time.sleep(0.1)
    board.WriteI2C(UB941AS,0x01,0x08) # Disable DSI
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0
    
    board.WriteI2C(UB941AS,0x4F,0x8C) # 4 Lane Mode continuous clock
    
    board.WriteI2C(UB941AS,0x5B,0x07) # Splitter mode
    
    board.WriteI2C(UB941AS,0x40,0x04) # DSI Indirect Registers DSI Port 0
    board.WriteI2C(UB941AS,0x41,0x05) # DPHY_SKIP_TIMING Register
    board.WriteI2C(UB941AS,0x42,0x4A) # TSKIP_CNT
    
    board.WriteI2C(UB941AS,0x56,0x80) # L/R Pixel Processing
    board.WriteI2C(UB941AS,0x32,0x80) # Set 2D Line Size 1920
    board.WriteI2C(UB941AS,0x33,0x07) # 
    
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0: 1920x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0x7F) 
    board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    board.WriteI2C(UB941AS,0x1E,0x02) # Select port 1: 1920x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0x7F) 
    board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    #Initialize internal DSI clock settings based on Power-up Sequence recommendations
    board.WriteI2C(UB941AS,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    
    board.WriteI2C(UB941AS,0x01,0x00) #Release DSI

    There are different formats for the input video (Left/Right 3D format, Alternate Line 3D format, and Alternate Pixel 3D format). I will attach an app note that gives more information on the Ux941 splitter mode operations.

    App note: Link

    Regards,
    Fadi A.

  • Hi Fadi

    DSI Continuous Clock Mode:

    • Continuous DSI clock mode

    DSI input mode:

    • Single-DSI mode

    DSI PORT:

    • DSI Input port0

    DSI number of LANES:

    •  4 lanes

     I try config SA8155 output 1920x720 size image ,and running 2 displays with resolution of 960x720, but can not display image.

    Besides, My screen supports 1920x720 and 960x720 resolutions.And the PCLK for both resolutions is exactly twice as high.

    I try the setting of  3840x720-Sym-Split-Script-Superframe_5F00_PCLK216.py .The phenomenon is the same as before(backlight is on, but panel not display image);

  • Hi Alex,

    Continuous DSI clock mode

    Yes, that's what I have in the script

    Single-DSI mode

    Yes, that's what I have in the script

    DSI Input port0

    Yes, that's what I have in the script

     4 lanes

    Yes, that's what I have in the script

     I try config SA8155 output 1920x720 size image ,and running 2 displays with resolution of 960x720, but can not display image.

    Is your superframe image 1920x720 and your 2 separate panels each one is 960x720? If that's the case can you try the modified script below. 

    The first script I sent you is configured for a side by side superframe (3840x720) running at PCLK = 216 MHz the superframe then gets cropped into 2 videos - each video has a resolution of 1920x720 at 108 MHz. 

    Modified Script - This script is for a side by side superframe (1920x720) running at PCLK = 108 MHz the superframe then gets cropped into 2 videos - each video has a resolution of 960x720 at 54 MHz. 

    1920x720 Sym Split Script Superframe_PCLK108.py
    # 1920x720@60 Symmetric Split Example - 2x 960x720@60
    
    # Video 0 and Video 1 Parameters:
    # HACT = 960
    # VACT = 720
    # PCLK = 54 MHz 
    
    # DSI Superframe Dimensions:
    # HACT = 1920
    # VACT = 720
    # PCLK = 108 MHz 
    
    # DSI clock = 324MHz
    # DSI Lane Speed = 648Mbps/lane 
    # 4 Lanes DSI
    # DSI input port 0
    # continuous clock
    # L/R Pixel Splitting
    
    
    import time
    
    UB941AS = 0x18
    
    board.WriteI2C(UB941AS,0x01,0x02) # Reset
    time.sleep(0.1)
    board.WriteI2C(UB941AS,0x01,0x08) # Disable DSI
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0
    
    board.WriteI2C(UB941AS,0x4F,0x8C) # 4 Lane Mode continuous clock (DSI Port0)
    
    board.WriteI2C(UB941AS,0x5B,0x07) # Splitter mode
    
    board.WriteI2C(UB941AS,0x40,0x04) # DSI Indirect Registers DSI Port 0
    board.WriteI2C(UB941AS,0x41,0x05) # DPHY_SKIP_TIMING Register
    board.WriteI2C(UB941AS,0x42,0x20) # TSKIP_CNT
    
    board.WriteI2C(UB941AS,0x56,0x80) # L/R Pixel Processing
    board.WriteI2C(UB941AS,0x32,0xC0) # Set 2D Line Size 960
    board.WriteI2C(UB941AS,0x33,0x03) # Set 2D Line Size 960
    
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0: 960x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0xBF) 
    board.WriteI2C(UB941AS,0x39,0x03) # X Stop = 959
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    board.WriteI2C(UB941AS,0x1E,0x02) # Select port 1: 960x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0xBF) 
    board.WriteI2C(UB941AS,0x39,0x03) # X Stop = 959
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    #Initialize internal DSI clock settings based on Power-up Sequence recommendations
    board.WriteI2C(UB941AS,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    
    board.WriteI2C(UB941AS,0x01,0x00) #Release DSI

    If this isn't what you are looking for, please send me a block diagram of the configuration you need, thanks. 

    Regards,
    Fadi A.

  • I try the setting of  1920x720-Sym-Split-Script-Superframe_5F00_PCLK108.py .The phenomenon is the same as before(backlight is on, but panel not display image);

  • Hey Alex,

    Few Things to clarify:

    3. config SA8155 output 1920x720 or 960x720 size image ,and config ub941 work in single FPD-LINK Transmitter mode, Panel0 can display image

    When you say it works in single FPD-Link Transmitter mode, are you talking about Internal PATGEN from 941AS to display or is does it work when using the SoC: Qcom SA8155 video output ? 

    What is the exact timing you were using here for the working case?

    4. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0xc,Panel0 can display image
    5. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0x8,Panel0 can not display image

    Difference between 0x8 and 0xC is toggling bit2 which selects the timing for the internal generated pattern. In Independent 2:2 mode, this controls the selected FPD-Link III port. which you could select through register 0x1E.

    0xC = The Pattern Generator creates its own video timing so uses internal timing from 941AS.

    0x8 = The Pattern Generator uses external timing from the pixel clock - This could indicate there is a pixel CLK issue from the SoC

    6. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0x8; 0x5b = 0x1,Panel0 can display image

    0x5b = 0x1 is forcing single FPD-Link  on Port0 only and disabling Port1 so that makes sense that you would only see display on panel0.

    In your case, you need to set 0x5B = 0x07 for Splitter mode.

    Regards,
    Fadi A.

  • Hi Fadi:

    When you say it works in single FPD-Link Transmitter mode, are you talking about Internal PATGEN from 941AS to display or is does it work when using the SoC: Qcom SA8155 video output ? 

    What is the exact timing you were using here for the working case?

    I've tested it both ways: PATGEN and SoC: Qcom SA8155 video output

    Difference between 0x8 and 0xC is toggling bit2 which selects the timing for the internal generated pattern. In Independent 2:2 mode, this controls the selected FPD-Link III port. which you could select through register 0x1E.

    Please refer to the picture below for setting of PATGEN. 0x1e = 0x1

    0x5b = 0x1 is forcing single FPD-Link  on Port0 only and disabling Port1 so that makes sense that you would only see display on panel0.

    In your case, you need to set 0x5B = 0x07 for Splitter mode.

    Yes, you right. I just want to test whether it is the problem of SOC: video output. According to the current phenomenon, there is no problem with SOC: video output, but we still cannot display it through split mode

  • Hi Alex,

    What Des do you use here?

    Can you send me the timing for the working panel?

    So you got Patgen from 941 as well as SoC video to work when using a single FPD port0 to display?

    Do you have access to ALP ?  If no can you download ALP and do you have USB2ANY or Ardvark that you can connect to local I2C of 929?

    I can't see this image it's blurry.

    Regards,
    Fadi A.

  • Hi Fadi:

    What Des do you use here?

    948

    Can you send me the timing for the working panel?

    1920*720@60

        uVisWidth        = '1920'
        uHsyncFrontPorch = '50'
        uHsyncWidth      = '50'
        uHsyncBackPorch  = '50'
        uVisHeight       = '720'
        uVsyncFrontPorch = '50'
        uVsyncWidth      = '50'
        uVsyncBackPorch  = '50'
        uPixelFreqInHz   = '108054000'
    So you got Patgen from 941 as well as SoC video to work when using a single FPD port0 to display?
    yes, i can display image.
    Do you have access to ALP ?  If no can you download ALP and do you have USB2ANY or Ardvark that you can connect to local I2C of 929?
    Sorry we don't have USB2ANY.
    Difference between 0x8 and 0xC is toggling bit2 which selects the timing for the internal generated pattern. In Independent 2:2 mode, this controls the selected FPD-Link III port. which you could select through register 0x1E.
    /*register,value*/
    0x01,0x02,
    0x01,0x08,
    0x5B,0x07,

    0x1E,0x01,
    0x66,0x1A,
    0x67,0x09, //M=9
    0x66,0x03,
    0x67,0x42, //

    0x66,0x04,
    0x67,0x0b, //least 8 bit of Total Horizontal frame size
    0x66,0x05,
    0x67,0x64, //Least 4 bit TV + Most 4 bit TH
    0x66,0x06,
    0x67,0x36, //Most 8 bit of Total Vertical frame size

    0x66,0x07,
    0x67,0xc0, //least 8 bit of active Horizontal frame size
    0x66,0x08,
    0x67,0x03, //Least 4 bit AV + Most 4 bit AH
    0x66,0x09,
    0x67,0x2D, //Most 8 bit of active Vertical frame size

    0x66,0x0A,
    0x67,0x16, //Horizontal Sync Width
    0x66,0x0B,
    0x67,0x32, //Vertical Sync Width
    0x66,0x0C,
    0x67,0x16, //Horizontal back porch
    0x66,0x0D,
    0x67,0x32, //Vertical back porch

    0x65,0x08, //using internal timing and internal clock
    0x64,0x05, //enable PG

    0x01,0x00, //enable DSI

    0x1E,0x01, //Select FPD-Link III Port 0
    0x07,0x58,
    0x08,0x5c,
    0x03,0x9a,

    0x1E,0x02, //Select FPD-Link III Port 0
    0x07,0x58,
    0x08,0x5E,
    0x03,0x9a,
    0x1E,0x04,
  • SOC video output:

    1920*720@60

        uVisWidth        = '1920'
        uHsyncFrontPorch = '50'
        uHsyncWidth      = '50'
        uHsyncBackPorch  = '50'
        uVisHeight       = '720'
        uVsyncFrontPorch = '50'
        uVsyncWidth      = '50'
        uVsyncBackPorch  = '50'
        uPixelFreqInHz   = '108054000'
    panel working timing:
    960*720@60
        uVisWidth        = '960'
        uHsyncFrontPorch = '25'
        uHsyncWidth      = '25'
        uHsyncBackPorch  = '25'
        uVisHeight       = '720'
        uVsyncFrontPorch = '50'
        uVsyncWidth      = '50'
        uVsyncBackPorch  = '50'
        uPixelFreqInHz   = '54027000'
  • Hey Alex,

    Can you run this script. 

    I have 941 and both 948 set to mode_Sel1 = 1 , mode_sel0=1.

    Auto-Detect FPD-Link III mode_941AS_1920_720_Per_Panel.py
    import time
    
    # timing for each panel is 1920*720@60
    # Total Horizontal = '2070'
    # uVisWidth        = '1920'
    # uHsyncFrontPorch = '50'
    # uHsyncWidth      = '50'
    # uHsyncBackPorch  = '50'
    # Total Vertical   = '870'
    # uVisHeight       = '720'
    # uVsyncFrontPorch = '50'
    # uVsyncWidth      = '50'
    # uVsyncBackPorch  = '50'
    # uPixelFreqInHz   = '108054000'
    
    
    Ser_addr = 0x18
    
    board.WriteI2C(Ser_addr,0x01,0x02) # Reset
    
    time.sleep(0.5)
    board.WriteI2C(Ser_addr,0x5B,0x00) #Set 941AS to Auto-Detect FPD-Link III mode (Single, Dual, or Replicate)
    
    board.WriteI2C(Ser_addr,0x1E,0x01)
    board.WriteI2C(Ser_addr,0x66,0x1A)
    board.WriteI2C(Ser_addr,0x67,0x01) #M=1
    board.WriteI2C(Ser_addr,0x66,0x03)
    board.WriteI2C(Ser_addr,0x67,0x02) #N=2
    
    board.WriteI2C(Ser_addr,0x66,0x04)
    board.WriteI2C(Ser_addr,0x67,0x16) #least 8 bit of Total Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x05)
    board.WriteI2C(Ser_addr,0x67,0x68) #Least 4 bit TV + Most 4 bit TH
    board.WriteI2C(Ser_addr,0x66,0x06)
    board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x07)
    board.WriteI2C(Ser_addr,0x67,0x80) #least 8 bit of active Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x08)
    board.WriteI2C(Ser_addr,0x67,0x07) #Least 4 bit AV + Most 4 bit AH
    board.WriteI2C(Ser_addr,0x66,0x09)
    board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x0A)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0B)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0C)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal back porch
    board.WriteI2C(Ser_addr,0x66,0x0D)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
    board.WriteI2C(Ser_addr,0x65,0x04) #using internal timing and internal clock
    board.WriteI2C(Ser_addr,0x64,0x15) #enable PG/color bars
    
    #0x01,0x00, #enable DSI
    
    board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
    board.WriteI2C(Ser_addr,0x08,0x5C) #0x08,0x5c
    board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0
    
    
    board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 1 0x1E,0x02, 
    board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
    board.WriteI2C(Ser_addr,0x08,0x5E) #0x08,0x5E
    board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
    board.WriteI2C(Ser_addr,0x1E,0x04) #0x1E,0x04
    
    
    

    Here are the results I got:

    Setup:

    Output: using a dual panel display, first 948 (port0) connected to left side panel, 2nd 948 (port1) connected to right side panel.

    Please try running the splitter script below - this is for internal timing and patgen (colorbar/red) and confirm the following:

    splitter_mode.py
    import time
    
    # timing for each panel is 1920*720@60
    # Total Horizontal = '2070'
    # uVisWidth        = '1920'
    # uHsyncFrontPorch = '50'
    # uHsyncWidth      = '50'
    # uHsyncBackPorch  = '50'
    # Total Vertical   = '870'
    # uVisHeight       = '720'
    # uVsyncFrontPorch = '50'
    # uVsyncWidth      = '50'
    # uVsyncBackPorch  = '50'
    # uPixelFreqInHz   = '108054000'
    
    
    Ser_addr = 0x18
    
    time.sleep(0.5)
    board.WriteI2C(Ser_addr,0x01,0x08) # Reset
    board.WriteI2C(Ser_addr,0x01,0x02) # Reset
    
    
    
    time.sleep(0.5)
    board.WriteI2C(Ser_addr,0x5B,0x07) #Set 941AS to Splitter mode
    
    board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x66,0x1A)
    board.WriteI2C(Ser_addr,0x67,0x01) #M=1
    board.WriteI2C(Ser_addr,0x66,0x03)
    board.WriteI2C(Ser_addr,0x67,0x02) #N=2
    
    board.WriteI2C(Ser_addr,0x66,0x04)
    board.WriteI2C(Ser_addr,0x67,0x16) #least 8 bit of Total Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x05)
    board.WriteI2C(Ser_addr,0x67,0x68) #Least 4 bit TV + Most 4 bit TH
    board.WriteI2C(Ser_addr,0x66,0x06)
    board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x07)
    board.WriteI2C(Ser_addr,0x67,0x80) #least 8 bit of active Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x08)
    board.WriteI2C(Ser_addr,0x67,0x07) #Least 4 bit AV + Most 4 bit AH
    board.WriteI2C(Ser_addr,0x66,0x09)
    board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x0A)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0B)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0C)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal back porch
    board.WriteI2C(Ser_addr,0x66,0x0D)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
    board.WriteI2C(Ser_addr,0x65,0x04) #using internal timing and internal clock
    board.WriteI2C(Ser_addr,0x64,0x15) #enable PG/color bars
    
    board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x66,0x1A)
    board.WriteI2C(Ser_addr,0x67,0x01) #M=1
    board.WriteI2C(Ser_addr,0x66,0x03)
    board.WriteI2C(Ser_addr,0x67,0x02) #N=2
    
    board.WriteI2C(Ser_addr,0x66,0x04)
    board.WriteI2C(Ser_addr,0x67,0x16) #least 8 bit of Total Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x05)
    board.WriteI2C(Ser_addr,0x67,0x68) #Least 4 bit TV + Most 4 bit TH
    board.WriteI2C(Ser_addr,0x66,0x06)
    board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x07)
    board.WriteI2C(Ser_addr,0x67,0x80) #least 8 bit of active Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x08)
    board.WriteI2C(Ser_addr,0x67,0x07) #Least 4 bit AV + Most 4 bit AH
    board.WriteI2C(Ser_addr,0x66,0x09)
    board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x0A)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0B)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0C)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal back porch
    board.WriteI2C(Ser_addr,0x66,0x0D)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
    board.WriteI2C(Ser_addr,0x65,0x04) #using internal timing and internal clock
    board.WriteI2C(Ser_addr,0x64,0x31) #enable PG/color bars
    
    #0x01,0x00, #enable DSI
    
    board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
    board.WriteI2C(Ser_addr,0x08,0x5C) #0x08,0x5c
    board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0
    
    
    board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 1 0x1E,0x02, 
    board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
    board.WriteI2C(Ser_addr,0x08,0x5E) #0x08,0x5E
    board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
    board.WriteI2C(Ser_addr,0x1E,0x04) #0x1E,0x04
    
    
    

    1- confirm you have Lock on both Des0 and Des1

    2- confirm the output matches the expected image below 

    output: using a dual panel display, first 948 (port0) connected to left side panel, 2nd 948 (port1) connected to right side panel.

    Regards,
    Fadi A.

  • Hi Fadi:

    I tried this script and the results are as follows:

    The result of Auto-Detect FPD-Link III mode_941AS_1920_720_Per_Panel.py:

    1. The screen cannot be displayed using this script

    2. Add 0x01 = 0x0 to this script, the screen can display image.

    The result of splitter_mode.py:

    1. The screen cannot be displayed using this script

    2. Add 0x01 = 0x0 to this script, the screen can display image. 

  • Hey Alex,

    That is because the DSI is held in reset state at the beginning of the script ... board.WriteI2C(Ser_addr,0x01,0x08) we forgot to release it (0x01 = 0x0

    Looks like the original script did have this release, but I forgot to add it to this one.

    Based on these results, this means the internal patgen with internal timing/clk is working as expected which means the issue is coming from the SoC side. 

    You can further narrow down the issue by doing the following:

    1- Run this script - this is set to internal patgen using external timing/CLK from SoC (if this doesn't work then it points to an external timing/CLK issue)

    splitter_mode_External_timing_CLK.py
    import time
    
    # timing for each panel is 1920*720@60
    # Total Horizontal = '2070'
    # uVisWidth        = '1920'
    # uHsyncFrontPorch = '50'
    # uHsyncWidth      = '50'
    # uHsyncBackPorch  = '50'
    # Total Vertical   = '870'
    # uVisHeight       = '720'
    # uVsyncFrontPorch = '50'
    # uVsyncWidth      = '50'
    # uVsyncBackPorch  = '50'
    # uPixelFreqInHz   = '108054000'
    
    
    Ser_addr = 0x18
    
    time.sleep(0.5)
    board.WriteI2C(Ser_addr,0x01,0x08) # Reset
    board.WriteI2C(Ser_addr,0x01,0x02) # Reset
    
    
    
    time.sleep(0.5)
    board.WriteI2C(Ser_addr,0x5B,0x07) #Set 941AS to Splitter mode
    
    board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x66,0x1A)
    board.WriteI2C(Ser_addr,0x67,0x01) #M=1
    board.WriteI2C(Ser_addr,0x66,0x03)
    board.WriteI2C(Ser_addr,0x67,0x02) #N=2
    
    board.WriteI2C(Ser_addr,0x66,0x04)
    board.WriteI2C(Ser_addr,0x67,0x16) #least 8 bit of Total Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x05)
    board.WriteI2C(Ser_addr,0x67,0x68) #Least 4 bit TV + Most 4 bit TH
    board.WriteI2C(Ser_addr,0x66,0x06)
    board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x07)
    board.WriteI2C(Ser_addr,0x67,0x80) #least 8 bit of active Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x08)
    board.WriteI2C(Ser_addr,0x67,0x07) #Least 4 bit AV + Most 4 bit AH
    board.WriteI2C(Ser_addr,0x66,0x09)
    board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x0A)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0B)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0C)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal back porch
    board.WriteI2C(Ser_addr,0x66,0x0D)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
    board.WriteI2C(Ser_addr,0x65,0x00) #using external timing and external clock
    board.WriteI2C(Ser_addr,0x64,0x15) #enable PG/color bars
    
    board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x66,0x1A)
    board.WriteI2C(Ser_addr,0x67,0x01) #M=1
    board.WriteI2C(Ser_addr,0x66,0x03)
    board.WriteI2C(Ser_addr,0x67,0x02) #N=2
    
    board.WriteI2C(Ser_addr,0x66,0x04)
    board.WriteI2C(Ser_addr,0x67,0x16) #least 8 bit of Total Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x05)
    board.WriteI2C(Ser_addr,0x67,0x68) #Least 4 bit TV + Most 4 bit TH
    board.WriteI2C(Ser_addr,0x66,0x06)
    board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x07)
    board.WriteI2C(Ser_addr,0x67,0x80) #least 8 bit of active Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x08)
    board.WriteI2C(Ser_addr,0x67,0x07) #Least 4 bit AV + Most 4 bit AH
    board.WriteI2C(Ser_addr,0x66,0x09)
    board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x0A)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0B)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0C)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal back porch
    board.WriteI2C(Ser_addr,0x66,0x0D)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
    board.WriteI2C(Ser_addr,0x65,0x00) #using external timing and external clock
    board.WriteI2C(Ser_addr,0x64,0x31) #enable PG/color bars
    
    
    board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
    board.WriteI2C(Ser_addr,0x08,0x5C) #0x08,0x5c
    board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0
    
    
    board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 1 0x1E,0x02, 
    board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
    board.WriteI2C(Ser_addr,0x08,0x5E) #0x08,0x5E
    board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
    board.WriteI2C(Ser_addr,0x1E,0x04) #0x1E,0x04
    
    board.WriteI2C(Ser_addr,0x01,0x00) #Release DSI
    

    2- Run this script - this is set to internal patgen using internal timing with external CLK (if this doesn't work then it points to an external pixel clock issue)

    splitter_mode_Internal_timing_External_CLK.py
    import time
    
    # timing for each panel is 1920*720@60
    # Total Horizontal = '2070'
    # uVisWidth        = '1920'
    # uHsyncFrontPorch = '50'
    # uHsyncWidth      = '50'
    # uHsyncBackPorch  = '50'
    # Total Vertical   = '870'
    # uVisHeight       = '720'
    # uVsyncFrontPorch = '50'
    # uVsyncWidth      = '50'
    # uVsyncBackPorch  = '50'
    # uPixelFreqInHz   = '108054000'
    
    
    Ser_addr = 0x18
    
    time.sleep(0.5)
    board.WriteI2C(Ser_addr,0x01,0x08) # Reset
    board.WriteI2C(Ser_addr,0x01,0x02) # Reset
    
    
    
    time.sleep(0.5)
    board.WriteI2C(Ser_addr,0x5B,0x07) #Set 941AS to Splitter mode
    
    board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x66,0x1A)
    board.WriteI2C(Ser_addr,0x67,0x01) #M=1
    board.WriteI2C(Ser_addr,0x66,0x03)
    board.WriteI2C(Ser_addr,0x67,0x02) #N=2
    
    board.WriteI2C(Ser_addr,0x66,0x04)
    board.WriteI2C(Ser_addr,0x67,0x16) #least 8 bit of Total Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x05)
    board.WriteI2C(Ser_addr,0x67,0x68) #Least 4 bit TV + Most 4 bit TH
    board.WriteI2C(Ser_addr,0x66,0x06)
    board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x07)
    board.WriteI2C(Ser_addr,0x67,0x80) #least 8 bit of active Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x08)
    board.WriteI2C(Ser_addr,0x67,0x07) #Least 4 bit AV + Most 4 bit AH
    board.WriteI2C(Ser_addr,0x66,0x09)
    board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x0A)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0B)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0C)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal back porch
    board.WriteI2C(Ser_addr,0x66,0x0D)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
    board.WriteI2C(Ser_addr,0x65,0x0C) #using internal timing and external clock
    board.WriteI2C(Ser_addr,0x64,0x15) #enable PG/color bars
    
    board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x66,0x1A)
    board.WriteI2C(Ser_addr,0x67,0x01) #M=1
    board.WriteI2C(Ser_addr,0x66,0x03)
    board.WriteI2C(Ser_addr,0x67,0x02) #N=2
    
    board.WriteI2C(Ser_addr,0x66,0x04)
    board.WriteI2C(Ser_addr,0x67,0x16) #least 8 bit of Total Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x05)
    board.WriteI2C(Ser_addr,0x67,0x68) #Least 4 bit TV + Most 4 bit TH
    board.WriteI2C(Ser_addr,0x66,0x06)
    board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x07)
    board.WriteI2C(Ser_addr,0x67,0x80) #least 8 bit of active Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x08)
    board.WriteI2C(Ser_addr,0x67,0x07) #Least 4 bit AV + Most 4 bit AH
    board.WriteI2C(Ser_addr,0x66,0x09)
    board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x0A)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0B)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0C)
    board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal back porch
    board.WriteI2C(Ser_addr,0x66,0x0D)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
    board.WriteI2C(Ser_addr,0x65,0x0C) #using internal timing and external clock
    board.WriteI2C(Ser_addr,0x64,0x31) #enable PG/color bars
    
    
    board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
    board.WriteI2C(Ser_addr,0x08,0x5C) #0x08,0x5c
    board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0
    
    
    board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 1 0x1E,0x02, 
    board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
    board.WriteI2C(Ser_addr,0x08,0x5E) #0x08,0x5E
    board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
    board.WriteI2C(Ser_addr,0x1E,0x04) #0x1E,0x04
    
    board.WriteI2C(Ser_addr,0x01,0x00) #Release DSI
    

    3- If above isn't enough to help you fix the issue - We have a DSI bring-up guide to debug issues with SoCs please see attached. 

    5100.DSI Bring up guid (1).pdf

    Make sure your SoC timing matches the timing I put into the above script. 

    Working timing:

    For the SoC script you can use this script

    2867.3840x720 Sym Split Script Superframe_PCLK216 (3).py
    # 3840x720@60 Symmetric Split Example - 2x 1920x720@60
    
    # Video 0 and Video 1 Parameters:
    # HACT = 1920
    # VACT = 720
    # PCLK = 108 MHz 
    
    # DSI Superframe Dimensions:
    # HACT = 3840
    # VACT = 720
    # PCLK = 216 MHz 
    
    # DSI clock = 648MHz
    # DSI Lane Speed = 1296Mbps/lane 
    # 4 Lanes DSI
    # DSI input port 0
    
    import time
    
    UB941AS = 0x18
    
    board.WriteI2C(UB941AS,0x01,0x02) # Reset
    time.sleep(0.1)
    board.WriteI2C(UB941AS,0x01,0x08) # Disable DSI
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0
    
    board.WriteI2C(UB941AS,0x4F,0x8C) # 4 Lane Mode continuous clock
    
    board.WriteI2C(UB941AS,0x5B,0x07) # Splitter mode
    
    board.WriteI2C(UB941AS,0x40,0x04) # DSI Indirect Registers DSI Port 0
    board.WriteI2C(UB941AS,0x41,0x05) # DPHY_SKIP_TIMING Register
    board.WriteI2C(UB941AS,0x42,0x4A) # TSKIP_CNT
    
    board.WriteI2C(UB941AS,0x56,0x80) # L/R Pixel Processing
    board.WriteI2C(UB941AS,0x32,0x80) # Set 2D Line Size 1920
    board.WriteI2C(UB941AS,0x33,0x07) # 
    
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0: 1920x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0x7F) 
    board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    board.WriteI2C(UB941AS,0x1E,0x02) # Select port 1: 1920x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0x7F) 
    board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    #Initialize internal DSI clock settings based on Power-up Sequence recommendations
    board.WriteI2C(UB941AS,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    
    board.WriteI2C(UB941AS,0x01,0x00) #Release DSI

    Regards,
    Fadi A.

  • Hi Fadi:

    4. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0xc,Panel0 can display image
    5. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0x8,Panel0 can not display image
    6. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0x8; 0x5b = 0x1,Panel0 can display image

    I had tried that using external timing/CLK from SoC, but panel cannot display image.

    if config 941 working in forcing single FPD-Link mode,and SOC video output has not change ,PATGEN work well . Based on these results,  i think there is no problem in soc side.

    Could you please help to guide us on what the problem is with soc side?

    I tried this scripts and the results are as follows:

    1. using splitter_mode_externel_timing_clk.py, config soc output 1920x720 size image ,panel cannot display image

    2. using splitter_mode_internal_timing_externel_clk.py, config soc output 1920x720 size image ,panel can display image

    3. using 2867.3840x720 Sym Split Script Superframe_PCLK216 (3).py, config soc output 3840x720 size image ,panel cannot display image

    1920*720@60

        uVisWidth        = '1920'
        uHsyncFrontPorch = '50'
        uHsyncWidth      = '50'
        uHsyncBackPorch  = '50'
        uVisHeight       = '720'
        uVsyncFrontPorch = '50'
        uVsyncWidth      = '50'
        uVsyncBackPorch  = '50'
        uPixelFreqInHz   = '108054000'

    3840*720@60

        uVisWidth        = '3840'
        uHsyncFrontPorch = '100'
        uHsyncWidth      = '100'
        uHsyncBackPorch  = '100'
        uVisHeight       = '720'
        uVsyncFrontPorch = '50'
        uVsyncWidth      = '50'
        uVsyncBackPorch  = '50'
        uPixelFreqInHz   = '216108000'
  • 1. using splitter_mode_externel_timing_clk.py, config soc output 1920x720 size image ,panel cannot display image

    2. using splitter_mode_internal_timing_externel_clk.py, config soc output 1920x720 size image ,panel can display image

    3. using 2867.3840x720 Sym Split Script Superframe_PCLK216 (3).py, config soc output 3840x720 size image ,panel cannot display image

    Based on these results,  the issue may is coming from the SoC timing.

    but using the same timing, why panel can display image when 941 working in  inforcing single FPD-Link mode?

  • Hey Alex,

    We need to get a register dump of the 941AS to review it. If possible can you provide the register dump of 941AS and 948? If you could do a dump during the run where you have a single panel0 working vs. when both panels aren't working ?

    config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0xc,Panel0 can display image
    • That is expected if your superframe image size outputted by SoC is 1920x720 --- if you want both displays to work correctly you need your superframe to be running at 3840x720 @  216 Mhz
    • When you say panel0 can display image , what is happening to panel1 ? Do you have Lock on panel1 but no video output or you don't have Lock?
    if config 941 working in forcing single FPD-Link mode,and SOC video output has not change ,PATGEN work well . Based on these results,  i think there is no problem in soc side.
    • Saying Patgen work well, what patgen are you referring to here? Is that the patgen coming from the SoC or you mean internal patgen from 941 ? 
    • Are you saying that when you force 941AS to single link mode you do see the SoC outputting video to the screen on panel0 ? What image size is the SoC sending as the superframe in this case?
     using splitter_mode_internal_timing_externel_clk.py, config soc output 1920x720 size image ,panel can display image
    • You are saying that SoC output 1920x720 image size? I thought the superframe image coming from the SoC was outputting 3840x720 size image?
    • Do you still see lock high on both Des0/1 when display can't output image?

    Please confirm that this is the timing that's programmed into the SoC and it's outputting as a superframe 3840x720 image running @ 216.108 mhz?

    3840*720@60
    uVisWidth        = '3840'
    uHsyncFrontPorch = '100'
    uHsyncWidth      = '100'
    uHsyncBackPorch  = '100'
    uVisHeight       = '720'
    uVsyncFrontPorch = '50'
    uVsyncWidth      = '50'
    uVsyncBackPorch  = '50'
    uPixelFreqInHz   = '216108000'

    What is the DSI CLk frequency?
    What is the DSI lane speed?
    but using the same timing, why panel can display image when 941 working in  inforcing single FPD-Link mode?

    If your SoC is sending a 1920x720 image @ 108 Mhz then when you force a single link it will work on port0 because it matches the expected timing coming from the SoC.

     

    Please confirm that this is your system block diagram 

    Regards,
    Fadi A.
  • I can't seem to reply to the last message. There is no dialog box when I click the reply button
    1. As I synced with you earlier, my panel supports two resolutions:1920x720 and 960x720
    1920x720:                                     960x720
    uVisWidth = '1920'                        uVisWidth = '960'
    uHsyncFrontPorch = '50'              uHsyncFrontPorch = '25'
    uHsyncWidth = '50'                       uHsyncWidth = '25'
    uHsyncBackPorch = '50'               uHsyncBackPorch = '25'
    uVisHeight = '720'                         uVisHeight = '720'
    uVsyncFrontPorch = '50'               uVsyncFrontPorch = '50'
    uVsyncWidth = '50'                       uVsyncWidth = '50'
    uVsyncBackPorch = '50'               uVsyncBackPorch = '50'
    uPixelFreqInHz = '108054000'      uPixelFreqInHz = '54027000'
    So, i tried split mode with superframe image size outputted by SoC is 1920x720 before ask this question to you. panel using 960x720 timing for display.

    5. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0x8,Panel0 can not display image
    6. config SA8155 output 1920x720 size image ,and config ub941 work in attern Generator, set 0x65 = 0x8; 0x5b = 0x1,Panel0 can display

    There , superframe image size outputted by SoC is 1920x720, and set 941 to internal patgen using external timing/CLK from SoC. in split mode, panel using 960x720 timing. In inforcing single FPD-Link mode, panel using 1920x720. So, i think there is no problem in soc side.

  • We need to get a register dump of the 941AS to review it. If possible can you provide the register dump of 941AS and 948? If you could do a dump during the run where you have a single panel0 working vs. when both panels aren't working ?

    both panels arenot working.txt
    superframe image size outputted by SoC is :
        uVisWidth        = '1920'
        uHsyncFrontPorch = '50'
        uHsyncWidth      = '50'
        uHsyncBackPorch  = '50'
        uVisHeight       = '720'
        uVsyncFrontPorch = '50'
        uVsyncWidth      = '50'
        uVsyncBackPorch  = '50'
    	
    reg dump:
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 18 00 00 9a 00 00 58 58 5c 01 41 00 07 30 00 00    ?..?..XX\?A.?0..
    10: 00 00 00 9f 00 00 fe 1e 7f 7f 01 00 04 00 04 00    ...?..?????.?.?.
    20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
    30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
    40: 10 94 00 00 00 00 00 00 00 00 00 00 00 00 00 8c    ??.............?
    50: 16 00 00 00 02 10 80 02 00 00 f9 07 07 06 44 35    ?...????..????D5
    60: 22 02 00 00 15 00 0d 32 00 00 00 00 00 00 20 00    "?..?.?2...... .
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7c 00    ..............|.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 82 00 38 00 00 64 40 00 00 00 00 02 ff 00    ..?.8..d@....??.
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 82 00 28 08 00 00 00 00 00 00 00 02 00 00    ..?.(?.......?..
    f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........	
    
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 58 04 00 f0 fe 1e 00 18 00 00 00 00 00 00 00 00    X?.???.?........
    10: 00 00 00 00 00 00 00 00 00 01 00 00 23 10 00 00    .........?..#?..
    20: 00 00 40 30 08 00 83 84 01 00 00 00 00 00 00 00    ..@0?.???.......
    30: 00 00 90 25 01 00 00 ac 00 00 00 07 20 e0 23 00    ..?%?..?...? ?#.
    40: 43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00    C??.`?..??.?..c.
    50: 03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00    ??.??....?  ....
    60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00    ....?...........
    70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........
    
    reg config:
     0x01,0x08, // Reset
     0x01,0x02, // Reset
    
     0x5B,0x07, //Set 941AS to Splitter mode
     0x56,0x80, //Set 941AS to Splitter mode
    
     0x1E,0x01, //Select FPD-Link III Port 0
     0x66,0x1A,
     0x67,0x01, //M=1
     0x66,0x03,
     0x67,0x02, //N=2
    
     0x66,0x04,
     0x67,0x0b, //least 8 bit of Total Horizontal frame size
     0x66,0x05,
     0x67,0x64, //Least 4 bit TV + Most 4 bit TH
     0x66,0x06,
     0x67,0x36, //Most 8 bit of Total Vertical frame size
    
     0x66,0x07,
     0x67,0xc0, //least 8 bit of active Horizontal frame size
     0x66,0x08,
     0x67,0x03, //Least 4 bit AV + Most 4 bit AH
     0x66,0x09,
     0x67,0x2D, //Most 8 bit of active Vertical frame size
    
     0x66,0x0A,
     0x67,0x16, //Horizontal Sync Width
     0x66,0x0B,
     0x67,0x32, //Vertical Sync Width
     0x66,0x0C,
     0x67,0x16, //Horizontal back porch
     0x66,0x0D,
     0x67,0x32, //Vertical back porch
     0x65,0x00, //using internal timing and internal clock
     0x64,0x15, //enable PG/color bars
    
     0x1E,0x02, //Select FPD-Link III Port 0
     0x66,0x1A,
     0x67,0x01, //M=1
     0x66,0x03,
     0x67,0x02, //N=2
    
     0x66,0x04,
     0x67,0x0b, //least 8 bit of Total Horizontal frame size
     0x66,0x05,
     0x67,0x64, //Least 4 bit TV + Most 4 bit TH
     0x66,0x06,
     0x67,0x36, //Most 8 bit of Total Vertical frame size
    
     0x66,0x07,
     0x67,0xc0, //least 8 bit of active Horizontal frame size
     0x66,0x08,
     0x67,0x03, //Least 4 bit AV + Most 4 bit AH
     0x66,0x09,
     0x67,0x2D, //Most 8 bit of active Vertical frame size
    
     0x66,0x0A,
     0x67,0x16, //Horizontal Sync Width
     0x66,0x0B,
     0x67,0x32, //Vertical Sync Width
     0x66,0x0C,
     0x67,0x16, //Horizontal back porch
     0x66,0x0D,
     0x67,0x32, //Vertical back porch
     0x65,0x00, //using internal timing and internal clock
     0x64,0x31, //enable PG/color bars
    
     0x01,0x00, //enable DSI
    
     0x1E,0x01, //Select FPD-Link III Port 0
     0x07,0x58, //0x07,0x58
     0x08,0x5C, //0x08,0x5c
     0x03,0x9A, //0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0
    
     0x1E,0x02, //Select FPD-Link III Port 1 0x1E,0x02, 
     0x07,0x58, //0x07,0x58
     0x08,0x5E, //0x08,0x5E
     0x03,0x9A, //0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
     0x1E,0x04, //0x1E,0x04

    single panel0 working.txt
    superframe image size outputted by SoC is :
        uVisWidth        = '1920'
        uHsyncFrontPorch = '50'
        uHsyncWidth      = '50'
        uHsyncBackPorch  = '50'
        uVisHeight       = '720'
        uVsyncFrontPorch = '50'
        uVsyncWidth      = '50'
        uVsyncBackPorch  = '50'
    	
    reg dump:
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 18 00 00 9a 00 00 58 58 5e 01 0c 00 07 30 00 00    ?..?..XX^??.?0..
    10: 00 00 00 9f 00 00 fe 1e 7f 7f 01 00 04 00 01 00    ...?..?????.?.?.
    20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
    30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
    40: 10 94 00 00 00 00 00 00 00 00 00 00 00 00 00 8c    ??.............?
    50: 16 00 00 00 02 10 00 02 00 00 d9 01 07 06 44 6a    ?...??.?..????Dj
    60: 22 02 00 00 31 00 0d 32 00 00 00 00 00 00 20 00    "?..1.?2...... .
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7c 00    ..............|.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 82 00 38 00 00 64 40 00 00 00 00 02 ff 00    ..?.8..d@....??.
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 82 00 28 08 00 00 00 00 00 00 00 02 00 00    ..?.(?.......?..
    f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
    
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 58 04 00 f0 fe 1e 00 18 00 00 00 00 00 00 00 00    X?.???.?........
    10: 00 00 00 00 00 00 00 00 00 01 00 00 23 19 99 99    .........?..#???
    20: 99 99 40 30 08 00 83 84 01 00 00 00 00 00 00 00    ??@0?.???.......
    30: 00 00 90 25 01 00 00 ac 00 00 00 06 20 e0 23 00    ..?%?..?...? ?#.
    40: 43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00    C??.`?..??.?..c.
    50: 03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00    ??.??....?  ....
    60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00    ....?...........
    70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........
    reg config:
     0x01,0x08, // Reset
     0x01,0x02, // Reset
    
     0x5B,0x01, //Set 941AS to Splitter mode
    
     0x1E,0x01, //Select FPD-Link III Port 0
     0x66,0x1A,
     0x67,0x01, //M=1
     0x66,0x03,
     0x67,0x02, //N=2
    
     0x66,0x04,
     0x67,0x16, //least 8 bit of Total Horizontal frame size
     0x66,0x05,
     0x67,0x68, //Least 4 bit TV + Most 4 bit TH
     0x66,0x06,
     0x67,0x36, //Most 8 bit of Total Vertical frame size
    
     0x66,0x07,
     0x67,0x80, //least 8 bit of active Horizontal frame size
     0x66,0x08,
     0x67,0x07, //Least 4 bit AV + Most 4 bit AH
     0x66,0x09,
     0x67,0x2D, //Most 8 bit of active Vertical frame size
    
     0x66,0x0A,
     0x67,0x16, //Horizontal Sync Width
     0x66,0x0B,
     0x67,0x32, //Vertical Sync Width
     0x66,0x0C,
     0x67,0x16, //Horizontal back porch
     0x66,0x0D,
     0x67,0x32, //Vertical back porch
     0x65,0x00, //using internal timing and internal clock
     0x64,0x15, //enable PG/color bars
    
     0x1E,0x02, //Select FPD-Link III Port 0
     0x66,0x1A,
     0x67,0x01, //M=1
     0x66,0x03,
     0x67,0x02, //N=2
    
     0x66,0x04,
     0x67,0x16, //least 8 bit of Total Horizontal frame size
     0x66,0x05,
     0x67,0x68, //Least 4 bit TV + Most 4 bit TH
     0x66,0x06,
     0x67,0x36, //Most 8 bit of Total Vertical frame size
    
     0x66,0x07,
     0x67,0x80, //least 8 bit of active Horizontal frame size
     0x66,0x08,
     0x67,0x07, //Least 4 bit AV + Most 4 bit AH
     0x66,0x09,
     0x67,0x2D, //Most 8 bit of active Vertical frame size
    
     0x66,0x0A,
     0x67,0x16, //Horizontal Sync Width
     0x66,0x0B,
     0x67,0x32, //Vertical Sync Width
     0x66,0x0C,
     0x67,0x16, //Horizontal back porch
     0x66,0x0D,
     0x67,0x32, //Vertical back porch
     0x65,0x00, //using internal timing and internal clock
     0x64,0x31, //enable PG/color bars
    
     0x01,0x00, //enable DSI
    
     0x1E,0x01, //Select FPD-Link III Port 0
     0x07,0x58, //0x07,0x58
     0x08,0x5C, //0x08,0x5c
     0x03,0x9A, //0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0
    
     0x1E,0x02, //Select FPD-Link III Port 1 0x1E,0x02, 
     0x07,0x58, //0x07,0x58
     0x08,0x5E, //0x08,0x5E
     0x03,0x9A, //0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
     0x1E,0x04, //0x1E,0x04

    Please confirm that this is the timing that's programmed into the SoC and it's outputting as a superframe 3840x720 image running @ 216.108 mhz

     try the setting of  splitter_mode_internal_timing_externel_clk.py when superframe image size outputted by SoC is 3840x720 .The phenomenon is the same as before(backlight is on, but panel not display image);

  • Hi Fadi:

    There is script: using internal timing clk to display image

    960x720_internal_timing_clk.txt
    superframe image size outputted by SoC is :
        uVisWidth        = '1920'
        uHsyncFrontPorch = '50'
        uHsyncWidth      = '50'
        uHsyncBackPorch  = '50'
        uVisHeight       = '720'
        uVsyncFrontPorch = '50'
        uVsyncWidth      = '50'
        uVsyncBackPorch  = '50'
    	
    reg dump:
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 18 00 00 9a 00 00 58 58 5c 01 0c 00 47 30 00 00    ?..?..XX\??.G0..
    10: 00 00 00 9f 00 00 fe 1e 7f 7f 01 00 04 00 04 00    ...?..?????.?.?.
    20: 0b 00 25 00 00 00 00 00 01 20 20 b0 00 00 a5 5a    ?.%.....?  ?..?Z
    30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
    40: 10 94 00 00 00 00 00 00 00 00 00 00 00 00 00 8c    ??.............?
    50: 16 00 00 00 02 10 80 02 04 00 f9 07 07 06 44 64    ?...?????.????Dd
    60: 22 02 00 00 15 04 0d 32 00 00 00 00 00 00 20 00    "?..???2...... .
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7c 00    ..............|.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 82 00 38 00 00 64 40 00 00 00 00 02 ff 00    ..?.8..d@....??.
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 82 00 28 08 00 00 00 00 00 00 00 02 00 00    ..?.(?.......?..
    f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
    
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 58 04 00 f0 fe 1e 00 18 00 00 00 00 00 00 00 00    X?.???.?........
    10: 00 00 00 00 00 00 00 00 00 01 00 00 23 10 99 99    .........?..#???
    20: 99 99 40 30 08 00 83 84 01 00 00 00 00 00 00 00    ??@0?.???.......
    30: 00 00 90 25 01 00 00 ac 00 00 00 07 20 e0 23 00    ..?%?..?...? ?#.
    40: 43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00    C??.`?..??.?..c.
    50: 03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00    ??.??....?  ....
    60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00    ....?...........
    70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........
    reg config:
     0x01,0x08, // Reset
     0x01,0x02, // Reset
    
     0x5B,0x07, //Set 941AS to Splitter mode
     0x56,0x80, //Set 941AS to Splitter mode
    
     0x1E,0x01, //Select FPD-Link III Port 0
     0x66,0x1A,
     0x67,0x01, //M=1
     0x66,0x03,
     0x67,0x02, //N=2
    
     0x66,0x04,
     0x67,0x0b, //least 8 bit of Total Horizontal frame size
     0x66,0x05,
     0x67,0x64, //Least 4 bit TV + Most 4 bit TH
     0x66,0x06,
     0x67,0x36, //Most 8 bit of Total Vertical frame size
    
     0x66,0x07,
     0x67,0xc0, //least 8 bit of active Horizontal frame size
     0x66,0x08,
     0x67,0x03, //Least 4 bit AV + Most 4 bit AH
     0x66,0x09,
     0x67,0x2D, //Most 8 bit of active Vertical frame size
    
     0x66,0x0A,
     0x67,0x16, //Horizontal Sync Width
     0x66,0x0B,
     0x67,0x32, //Vertical Sync Width
     0x66,0x0C,
     0x67,0x16, //Horizontal back porch
     0x66,0x0D,
     0x67,0x32, //Vertical back porch
     0x65,0x04, //using internal timing and internal clock
     0x64,0x15, //enable PG/color bars
    
     0x1E,0x02, //Select FPD-Link III Port 0
     0x66,0x1A,
     0x67,0x01, //M=1
     0x66,0x03,
     0x67,0x02, //N=2
    
     0x66,0x04,
     0x67,0x0b, //least 8 bit of Total Horizontal frame size
     0x66,0x05,
     0x67,0x64, //Least 4 bit TV + Most 4 bit TH
     0x66,0x06,
     0x67,0x36, //Most 8 bit of Total Vertical frame size
    
     0x66,0x07,
     0x67,0xc0, //least 8 bit of active Horizontal frame size
     0x66,0x08,
     0x67,0x03, //Least 4 bit AV + Most 4 bit AH
     0x66,0x09,
     0x67,0x2D, //Most 8 bit of active Vertical frame size
    
     0x66,0x0A,
     0x67,0x16, //Horizontal Sync Width
     0x66,0x0B,
     0x67,0x32, //Vertical Sync Width
     0x66,0x0C,
     0x67,0x16, //Horizontal back porch
     0x66,0x0D,
     0x67,0x32, //Vertical back porch
     0x65,0x04, //using internal timing and internal clock
     0x64,0x31, //enable PG/color bars
    
     0x01,0x00, //enable DSI
    
     0x1E,0x01, //Select FPD-Link III Port 0
     0x07,0x58, //0x07,0x58
     0x08,0x5C, //0x08,0x5c
     0x03,0x9A, //0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0
    
     0x1E,0x02, //Select FPD-Link III Port 1 0x1E,0x02, 
     0x07,0x58, //0x07,0x58
     0x08,0x5E, //0x08,0x5E
     0x03,0x9A, //0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
     0x1E,0x04, //0x1E,0x04

  • Hi Fadi:

    base on both panels arenot working.txt, add 948 config : 0x1d = 0x19 0x1e-0x21 = 0x99.The phenomenon is the same as before(backlight is on, but panel not display image)

  • Hey Alex,

    Let's take a step back and focus on the SoC debug for now and not worry about patgen from 941 since it seems that to both displays work fine when using internal timing with patgen from 941AS. 

    Can you provide a register dump for the main page registers as well as the indirect page registers when using the SoC script, not the internal patgen script - the above register dumps you provided are all main page registers only and running with the patgen script.

     SoC script with output image of 1920x720 - each panel is set to 960x720

    1920x720 Sym Split Script Superframe_PCLK108 (2).py
    # 1920x720@60 Symmetric Split Example - 2x 960x720@60
    
    # Video 0 and Video 1 Parameters:
    # HACT = 960
    # VACT = 720
    # PCLK = 54 MHz 
    
    # DSI Superframe Dimensions:
    # HACT = 1920
    # VACT = 720
    # PCLK = 108 MHz 
    
    # DSI clock = 324MHz
    # DSI Lane Speed = 648Mbps/lane 
    # 4 Lanes DSI
    # DSI input port 0
    # continuous clock
    # L/R Pixel Splitting
    
    
    import time
    
    UB941AS = 0x18
    
    board.WriteI2C(UB941AS,0x01,0x02) # Reset
    time.sleep(0.1)
    board.WriteI2C(UB941AS,0x01,0x08) # Disable DSI
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0
    
    board.WriteI2C(UB941AS,0x4F,0x8C) # 4 Lane Mode continuous clock (DSI Port0)
    
    board.WriteI2C(UB941AS,0x5B,0x07) # Splitter mode
    
    board.WriteI2C(UB941AS,0x40,0x04) # DSI Indirect Registers DSI Port 0
    board.WriteI2C(UB941AS,0x41,0x05) # DPHY_SKIP_TIMING Register
    board.WriteI2C(UB941AS,0x42,0x20) # TSKIP_CNT
    
    board.WriteI2C(UB941AS,0x56,0x80) # L/R Pixel Processing
    board.WriteI2C(UB941AS,0x32,0xC0) # Set 2D Line Size 960
    board.WriteI2C(UB941AS,0x33,0x03) # Set 2D Line Size 960
    
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0: 960x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0xBF) 
    board.WriteI2C(UB941AS,0x39,0x03) # X Stop = 959
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    board.WriteI2C(UB941AS,0x1E,0x02) # Select port 1: 960x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0xBF) 
    board.WriteI2C(UB941AS,0x39,0x03) # X Stop = 959
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    #Initialize internal DSI clock settings based on Power-up Sequence recommendations
    board.WriteI2C(UB941AS,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    
    board.WriteI2C(UB941AS,0x01,0x00) #Release DSI

    SoC script with output image of 3840x720 - each panel is set to 1920x720

    3840x720 Sym Split Script Superframe_PCLK216 (4).py
    # 3840x720@60 Symmetric Split Example - 2x 1920x720@60
    
    # Video 0 and Video 1 Parameters:
    # HACT = 1920
    # VACT = 720
    # PCLK = 108 MHz 
    
    # DSI Superframe Dimensions:
    # HACT = 3840
    # VACT = 720
    # PCLK = 216 MHz 
    
    # DSI clock = 648MHz
    # DSI Lane Speed = 1296Mbps/lane 
    # 4 Lanes DSI
    # DSI input port 0
    
    import time
    
    UB941AS = 0x18
    
    board.WriteI2C(UB941AS,0x01,0x02) # Reset
    time.sleep(0.1)
    board.WriteI2C(UB941AS,0x01,0x08) # Disable DSI
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0
    
    board.WriteI2C(UB941AS,0x4F,0x8C) # 4 Lane Mode continuous clock
    
    board.WriteI2C(UB941AS,0x5B,0x07) # Splitter mode
    
    board.WriteI2C(UB941AS,0x40,0x04) # DSI Indirect Registers DSI Port 0
    board.WriteI2C(UB941AS,0x41,0x05) # DPHY_SKIP_TIMING Register
    board.WriteI2C(UB941AS,0x42,0x4A) # TSKIP_CNT
    
    board.WriteI2C(UB941AS,0x56,0x80) # L/R Pixel Processing
    board.WriteI2C(UB941AS,0x32,0x80) # Set 2D Line Size 1920
    board.WriteI2C(UB941AS,0x33,0x07) # 
    
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0: 1920x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0x7F) 
    board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    board.WriteI2C(UB941AS,0x1E,0x02) # Select port 1: 1920x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0x7F) 
    board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    #Initialize internal DSI clock settings based on Power-up Sequence recommendations
    board.WriteI2C(UB941AS,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    
    board.WriteI2C(UB941AS,0x01,0x00) #Release DSI

    Can you fill-out the yellow highlighted boxes in the tracking sheet below. This way we'll keep the debug more organized. 

    The idea here is to collect more information about the register status, lock signal status (can be checked on Des side from registers 0x1C[0] or if you have a pin out you can probe it). We also need to know whether the lock is high and timing is getting to Des1 correctly while screen is black or no link at all, etc. 

    941AS_Tracking_Sheet.xlsx

    Regards,
    Fadi A.

  • HI Fadi:

    Base on 941AS_Tracking_Sheet.xlsx, two new configurations have been added:

    1. 960x720 port0 force  Script

    2. 1920x720 port0 force  Script

    the reason is:

    1. i tired the setting of  1920x720 port0 force  Script and 3840x720 port0 force  Script .The phenomenon is the same as before(backlight is on, but panel not display image)

    2. my panel supports two resolutions:1920x720 and 960x720

    941AS_Tracking_Sheet_New.xlsx

  • Hi Luo, 

    Monday, May 29th is a US public holiday, we will resume activity on this thread beginning Tuesday. Thanks for your patience. 

    Regards, 
    Logan

  • Hi Luo, 

    Fadi is OOO the rest of this week, so I'll be taking over this activity in the meantime. Thanks for your patience. 

    It is unclear per the tracking sheet what the underlying status of each test currently is. Can you fill out the yellow boxes in the last table you sent?

    Regards, 

    Logan

  • I have filled in the content of the yellow box, please refer to it:

    941AS_Tracking_Sheet_New.xlsx

  • Hi lou, 

    Apologies, I must have open one of the prior versions. I'll review and provide feedback by tomorrow. 

    Regards, 

    Logan

  • Hi Lou, 

    The following app note will help here with symmetrical splitting as well for reference. Splitter Mode Of 941

    After looking at your data, it is not clear what the issue is here. Your script "3840x720 Sym Split Script Superframe 216Mhz" looks correct. It is close to the below proven script also for 3840x720 symmetrical superframe. 

    Can you try lowering your PCLK? These devices are actually only rated up to 105MHz PCLK, and you are trying 108MHz. Can the blanking size be reduced?

    Regards, 

    Logan

  • HI Logan:

    Config SA8155 output 1920x720 size image, and config ub941 work in inforcing single FPD-Link mode, Panel0 can display, panel working in1920x720 timing

    Config SA8155 output 1920x720 size image, and config ub941 work in split mode, Panel0 cannot display image, panel working in 960x720 timing

    1. As I synced with you earlier, my panel supports two resolutions:1920x720 and 960x720
    1920x720:                                     960x720
    uVisWidth = '1920'                        uVisWidth = '960'
    uHsyncFrontPorch = '50'              uHsyncFrontPorch = '25'
    uHsyncWidth = '50'                       uHsyncWidth = '25'
    uHsyncBackPorch = '50'               uHsyncBackPorch = '25'
    uVisHeight = '720'                         uVisHeight = '720'
    uVsyncFrontPorch = '50'               uVsyncFrontPorch = '50'
    uVsyncWidth = '50'                       uVsyncWidth = '50'
    uVsyncBackPorch = '50'               uVsyncBackPorch = '50'
    uPixelFreqInHz = '108054000'      uPixelFreqInHz = '54027000'
  • Hi Lou, 

    Below is the script I was referring to above. 

    3840x720 Sym Split Script (3).py
    # 3840x720@60 Symmetric Split Example - 2x 1920x720@60
    
    # Video 0 and Video 1 Parameters:
    # HACT = 1920
    # HFP = 64
    # HSYNC = 32
    # HBP = 32
    # VACT = 720
    # VFP = 45
    # VSYNC = 8
    # VBP = 8
    # PCLK = 96MHz 
    
    # DSI Superframe Dimensions:
    # HACT = 3840
    # HFP = 128
    # HSYNC = 64
    # HBP = 64
    # VACT = 720
    # VFP = 45
    # VSYNC = 8
    # VBP = 8
    # PCLK = 192MHz 
    
    # DSI clock = 576MHz
    # DSI Lane Speed = 1152Mbps/lane 
    # 4 Lanes DSI
    # DSI input port 0
    
    import time
    
    UB941AS = 0x18
    
    board.WriteI2C(UB941AS,0x01,0x02) # Reset
    time.sleep(0.1)
    board.WriteI2C(UB941AS,0x01,0x08) # Disable DSI
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0
    
    board.WriteI2C(UB941AS,0x4F,0x8C) # 4 Lane Mode continuous clock
    
    board.WriteI2C(UB941AS,0x5B,0x07) # Splitter mode
    
    board.WriteI2C(UB941AS,0x40,0x04) # TSKIP_CNT
    board.WriteI2C(UB941AS,0x41,0x05) # TSKIP_CNT
    board.WriteI2C(UB941AS,0x42,0x40) # TSKIP_CNT
    
    board.WriteI2C(UB941AS,0x56,0x80) # L/R Pixel Processing
    board.WriteI2C(UB941AS,0x32,0x80) # Set 2D Line Size 1920
    board.WriteI2C(UB941AS,0x33,0x07) # 
    
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0: 1920x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0x7F) 
    board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    board.WriteI2C(UB941AS,0x1E,0x02) # Select port 1: 1920x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0x7F) 
    board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    board.WriteI2C(UB941AS,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    
    board.WriteI2C(UB941AS,0x01,0x00) #Release DSI

    I do not see any issue with your version aside from the PCLK setpoints.

    Are you sure there isn't an issue with SoC output when outputting the higher PCLK full resolution superframe vs the smaller frames that are working?

    Regards, 

    Logan

  • Config SA8155 output 1920x720 size image, and config ub941 work in inforcing single FPD-Link mode, Panel0 can display, panel working in1920x720 timing

    Config SA8155 output 1920x720 size image, and config ub941 work in split mode, Panel0 cannot display image, panel working in 960x720 timing

    Base on this result,  I do not the issue is due to SoC output. In this scenarios, there is no change with Soc output

  • Hey Alex,

    Thanks for collecting the data. let me review the register dumps, and tracking sheet and get back to you tomorrow. 

    Regards,
    Fadi A.

  • Hey Alex,

    I'm still reviewing the register dumps, It could that since the 948 runs at a slower PCLK than 941AS we may need to adjust your PCLK to get it working with your resolution.

    948 PCLK Spec:

    Let's see if we can get the lower resolution to work with internal patgen using internal timing/clk and we'll move to the next step.

    Can you try running this script?

    5047.splitter_mode_960_720_Internal_PG_50Mhz.py
    import time
    
    # timing for each panel is:
    #960*720@60
    #uVisWidth        = '960'
    #uHsyncFrontPorch = '25'
    #uHsyncWidth      = '25'
    #uHsyncBackPorch  = '25'
    #uVisHeight       = '720'
    #uVsyncFrontPorch = '50'
    #uVsyncWidth      = '50'
    #uVsyncBackPorch  = '50'
    #uPixelFreqInHz   = '50 Mhz
    
    
    
    Ser_addr = 0x18
    
    time.sleep(0.5)
    board.WriteI2C(Ser_addr,0x01,0x08) # Reset
    board.WriteI2C(Ser_addr,0x01,0x02) # Reset
    
    
    
    time.sleep(0.5)
    board.WriteI2C(Ser_addr,0x5B,0x07) #Set 941AS to Splitter mode
    
    board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x66,0x1A)
    board.WriteI2C(Ser_addr,0x67,0x01) #M=1
    board.WriteI2C(Ser_addr,0x66,0x03)
    board.WriteI2C(Ser_addr,0x67,0x04) #N=4
    
    board.WriteI2C(Ser_addr,0x66,0x04)
    board.WriteI2C(Ser_addr,0x67,0x0B) #least 8 bit of Total Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x05)
    board.WriteI2C(Ser_addr,0x67,0x64) #Least 4 bit TV + Most 4 bit TH
    board.WriteI2C(Ser_addr,0x66,0x06)
    board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x07)
    board.WriteI2C(Ser_addr,0x67,0xC0) #least 8 bit of active Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x08)
    board.WriteI2C(Ser_addr,0x67,0x03) #Least 4 bit AV + Most 4 bit AH
    board.WriteI2C(Ser_addr,0x66,0x09)
    board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x0A)
    board.WriteI2C(Ser_addr,0x67,0x19) #Horizontal Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0B)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0C)
    board.WriteI2C(Ser_addr,0x67,0x19) #Horizontal back porch
    board.WriteI2C(Ser_addr,0x66,0x0D)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
    
    board.WriteI2C(Ser_addr,0x65,0x04) #using internal timing and internal clock
    board.WriteI2C(Ser_addr,0x64,0x15) #enable PG/color bars
    
    board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 1
    board.WriteI2C(Ser_addr,0x66,0x1A)
    board.WriteI2C(Ser_addr,0x67,0x01) #M=1
    board.WriteI2C(Ser_addr,0x66,0x03)
    board.WriteI2C(Ser_addr,0x67,0x04) #N=4
    
    board.WriteI2C(Ser_addr,0x66,0x04)
    board.WriteI2C(Ser_addr,0x67,0x0B) #least 8 bit of Total Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x05)
    board.WriteI2C(Ser_addr,0x67,0x64) #Least 4 bit TV + Most 4 bit TH
    board.WriteI2C(Ser_addr,0x66,0x06)
    board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x07)
    board.WriteI2C(Ser_addr,0x67,0xC0) #least 8 bit of active Horizontal frame size
    board.WriteI2C(Ser_addr,0x66,0x08)
    board.WriteI2C(Ser_addr,0x67,0x03) #Least 4 bit AV + Most 4 bit AH
    board.WriteI2C(Ser_addr,0x66,0x09)
    board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size
    
    board.WriteI2C(Ser_addr,0x66,0x0A)
    board.WriteI2C(Ser_addr,0x67,0x19) #Horizontal Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0B)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
    board.WriteI2C(Ser_addr,0x66,0x0C)
    board.WriteI2C(Ser_addr,0x67,0x19) #Horizontal back porch
    board.WriteI2C(Ser_addr,0x66,0x0D)
    board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
    
    board.WriteI2C(Ser_addr,0x65,0x04) #using internal timing and internal clock
    board.WriteI2C(Ser_addr,0x64,0x31) #enable PG/red
    
    
    board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
    board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
    board.WriteI2C(Ser_addr,0x08,0x5C) #0x08,0x5c
    board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0
    
    
    board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 1 0x1E,0x02, 
    board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
    board.WriteI2C(Ser_addr,0x08,0x5E) #0x08,0x5E
    board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
    board.WriteI2C(Ser_addr,0x1E,0x04) #0x1E,0x04
    
    
    board.WriteI2C(Ser_addr,0x01,0x00) #Release DSI

    Regards,
    Fadi A.