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DS90UB954-Q1: I2C communication with slave device through DS90UB953-Q1

Part Number: DS90UB954-Q1
Other Parts Discussed in Thread: DS90UB953-Q1, , ALP

Hi team,

SOC utilizes I2C to communicate with slave devices through DS90UB954-Q1-->DS90UB953-Q1, with a low probability of reading error values

Testing the same command 1000 times will result in one error, and the command speed is 60 times per second

The instruction is 6 bytes, consisting of Address, Command, Data, Data, Data, and Data. The error value is randomly generated in a certain byte, and each exception Byte reads the same value

Currently, I2C mode is set to Standard, and 0X58 in DS90UB954-Q1 is set to 5E

Attempted to SOC fly wire I2C to Slave Device, skipped DS90UB953-Q1, tested 10000 times without any abnormalities

Reading the value of the 954 0x4D register is 0x3

What may be the problem with this phenomenon? Could you please provide some troubleshooting suggestions

Best Regards,

Amy Luo

  • Hi Amy,

    • Can you please provide a register dump of the 954 and 953 in the case where you see the I2C error? Back channel errors would appear on the 953 and are reported in register 0x52. 
    • If you read 954 Reg 0x4D multiple times throughout operation and after you get the I2C error value, does it always stay at 0x03? 
      • To see whether LOCK drop is causing the incorrect I2C transaction, you can also probe the LOCK status on a GPIO pin and check whether it goes low whenever you see the I2C issue.
    • Are you able to run the MAP tool on ALP to check the link margin quality?

    Regards,

    Cindy

  • Hi Cindy,

    Glad to see your reply. Regarding your above question, once I receive a response from the customer, I will share it with you.

    Here is the latest testing situation from the customer:

    When DS90UB954-Q1 mode is Non synchronous mode, I2C may encounter a probability of abnormal reading value.

    Modify DS90UB954-Q1 mode to Synchronous mode, testing 500000 times without receiving any abnormalities.

    Since these two modes are related to the CLK_IN of DS90UB953-Q1, may I ask if the transmission I2C signal needs to be set to Synchronous mode?

    Regards,

    Amy

  • Hi Amy,

    You can send I2C transactions in any mode. One key difference is that non-synchronous mode has a back channel of 10Mbps whereas synchronous mode has a back channel of 50 Mbps. This affects the BCC delay in I2C throughput calculations, but I2C throughput is mainly dominated by the I2C speed configuration (see 7.5.3.1 Remote I2C Targets Data Throughput).

    If they are able to use the MAP tool, they can also compare the link quality between sync mode and non-sync mode as there may be a difference in the link margin between the two modes that is causing this behavior.

    Once you get the register dumps and the other information I can look over that as well. 

    Regards,

    Cindy

  • Hi Cindy,

    Thanks for your information. Regarding the I2C error, the customer suspects that it is related to the 954 953 OSC frequency offset.

    Currently, the customer is using synchronous mode instead.

  • Hi Amy,

    Thank you for letting me know. In that case, I will close out this thread but feel free to submit another one if you have more questions. 

    Regards,

    Cindy