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TDP0604: Default I2C mode setting value

Part Number: TDP0604

Hi,

I had design TDP0604 for HDMI2.0 output.

I set control method to I2C control mode.

But I did not find these parameter default value. Please help to provide this information, thanks.

1) Lane swap. Normal or reverse

2) Receiver EQ value

3) TX emphasis value

4) TX Swing voltage

5) Termination value

6) Transmitter Impedance control

7) TX slew rate

Project Information

Project name: PCM-8728

Platform: Intel RPL-S CPU + R680E PCH

Regards,

Harry Wang

2023/05/25

  • Hi Harry,

    Please see below:

    1. Lane Swap is controlled by MISC_CONTROL (Offset = Ah) [Reset = 08h] bit 7 LANE_SWAP = 0h. Defaults to no lanes swapped.

    2. Receiver EQ value is controlled by three registers

     -D0_CONFIG2 (Offset = 15h) [Reset = 00h]

     -D1_CONFIG2 (Offset = 17h) [Reset = 00h]

     -D2_CONFIG2 (Offset = 19h) [Reset = 00h]

     bits 3-0 Dx_EQ = 0h. Defaults to min EQ setting.

    3&4. TX Emphasis value and swing voltage are controlled by three registers

     -D0_CONFIG1 (Offset = 14h) [Reset = 03h]

     -D1_CONFIG1 (Offset = 16h) [Reset = 03h]

     -D2_CONFIG1 (Offset = 18h) [Reset = 03h]

     bits 6-4 Dx_TXFFE = 0h (controls emphasis - defaults to 0.0dB) and bits 2-0 Dx_VOD = 3h (controls swing voltage - defaults to limited 1000mV linear 1200mV)

    5&6. Termination value and transmitter impedance control are controlled by GBL_CTRL1 (Offset = Dh) [Reset = 22h] bit 1-0 TERM = 2h. Defaults to automatically set a value according to which HDMI mode it is operating in.

    7. TX slew rate is controlled by GBL_SLEW_CTRL (Offset = Bh) [Reset = 34h] bits 2-0 SLEW_6G = 4h (defaults to mid edge rate) and GBL_SLEW_CTRL1 (Offset = Ch) [Reset = 71h] bits 2-0 SLEW_CLK = 1h (defaults to slow edge rate).

    Thanks, Allison

  • Dear Allison

    This answer is clear to me.

    Thanks

    Harry Wang

    2023/05/26