• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 76 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83TG720S-Q1: Several timing related issues

Alan Xia
Expert 4415 points
Part Number: DP83TG720S-Q1

Hi team，

1、Does the chip DP83TG720SWCST Q1 need at least two external power supplies, 3.3V and 1.0V?Does the chip DP83TG720SWCST Q1 need at least two external power supplies, 3.3V and 1.0V? Is there no power-up sequence requirement?

...

2、Is there any requirement for the time from 3.3V and 1.0V to reset release? Or does the reset pin need to be pulled high when the power is first turned on?

3.、Are there timing requirements for VDDIO, VDD1P0, VDDA, and VSLEEP?
4.、Do the reset signals of VDDIO, VDD1P0, VDDA, and VSLEEP need to be pulled high all the time during the power-on phase? Or pull low first and then pull high? Or is it pulled high first, then pulled low, and then pulled high again?

  • 0
    TI__Mastermind 27915 points

    Hello,

    1) DP83TG720 needs a 3.3V and 1.0V at best. However it should be noted that if required, the VDDIO rail can be 1.8V and 2.5V. Vsleep should also be a separate supply if sleep functionality is being used.

    2) Reset is expected to be pulled high when PHY is powered on.

    3) Please see section 6.6 for requirements.

    4) Unsure what you mean by reset signals of each rail. These rails do not have a reset component.

    Sincerely,

    Gerome