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DP83TC814R-Q1: Boot strap latch in timing

Part Number: DP83TC814R-Q1

Hello Expert,

I'd like to know about the Boot strap latch-in timing when they after release RESET_N after VDD supplied.
Their RESET_N release timing is as follows.

For the case of RESET_N and VDD supply becoming high simultaneously, The time to loaded strap setting for PHY is defined as T5.6 and which is 10ms(Max).
For the case of RESET_N becoming high after VDD supplied, The time to loaded strap setting  is seems T6.2(1ms).
However T6.2 only have minimum value so I'd like to know about the maximum value.
I suppose that latch-in timing must be completed with in T6.4(1.8ms maximum).
Is this understanding correct?
Or could we apply T5.6 for this case?

Best regards,
Kazuki Kuramochi