Hi Team,
Please tell me about the Power-Down Sequence of the XIO 2001.
The data sheet states that power must be removed after asserting PERST # and stopping REFCLK.
However, in our design, Vdd_33 starts falling down about 90us faster than PERST # and REFCLK.
Can this damage the XIO2001?
*From the following thread, it was recognized that there is no problem to assert PERST # and stop REFCLK at the same time.
e2e.ti.com/.../xio2001-power-down-sequence-query-modifications
Best Regards,
Kobayashi