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DS90UB927Q-Q1: abnormal phenomenon with DS90UB927+DS90UB940

Part Number: DS90UB927Q-Q1

Hello,

 One customer met one question during using DS90UB927+DS90UB940. The application is  HOST(LVDS/I2C)--927--940--(CSI/I2C) display. 

Now one strange phenomenon is that once 927 connected 940, then 927 is always send 0xD7 and didn't stop to send 0XD7.  Even disconnected the Host and Display, he tested the 927 still send 0XD7. Below is the captured data with Logic Analyzer.

So the questions are as these:

1. He cleared the CRC error by 0X4 bit5, and found that if connected 940, 924 still send 0xD7 data.

2. Why 927 would send 0xD7 or 0XD4 data ? He debugged that if he set Back Channel CRC Generator Enable(0x3=0XB0)  of DS90UB940,  927 would stop send 0xD7 or send once every 128ms, or send again after 10s. That is not completely resolved, what is the reason about this?  

3. If there is any way or registers to disable 927 to send data when 927 connected 940? 

Best regards

Kailyn

  • Hi Kailyn,

    I would like to confirm the customer's setup and add clarity to where the I2C issue is being experienced.

    1. Is the diagram above the correct representation of the system?

    2. The I2C issue being experienced is between the 927 and 940, over FPD-Link?

    3. The SoC with LVDS and I2C is connected over I2C port I2C0 and the display is also connected to the deserializer over I2C0?

    It looks like bit 5 of the 0x04 register on the 927 controls "Clear back channel CRC Error Counters", which may clear the counter of errors on the system and not the errors themselves.

    The assignment of 0xB0 to the register 0x03 would enable the back-channel CRC checker, I2C remote write auto acknowledge, and filter enable. With these settings, pulses with less than two full PCLK cycles (1/2 the PCLK frequency) are rejected, and I2C auto acknowledge will not wait for the deserializer (940) to acknowledge writes to devices. Can we confirm that the I2C communication bug is happening between the 927 and 940? Also, what is the frequency of the PCLK between the devices?

    Please let me know if the understanding of the system configurations is correct.

    Best,

    Miguel