• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 32 subscribers
  • Views 455 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DS125DF410: PRBS output with free-running VCO

DS125DF410: Using PRBS and free running VCO to create CDR lock between two retimers on different boards

Jon Wick
Prodigy 10 points
Part Number: DS125DF410

Hi all, I am trying to develop a loopback tester using 2 different retimer devices on two different boards. The goal is to be able to generate a CDR lock between the devices without a host to lock onto for a stable frequency reference.

I have board 1 configured to generate a PRBS-9 sequence, while free running the VCO, and I have board 2 set to the default 10.3125 Gbps configuration.

When connected to my host, I am able to obtain a lock and monitor eye diagrams, but I am unable to obtain a lock when using board 1 to generate a free running sequence.

I am monitoring address 2 of each channel to get a status of the receiver (board 2).

I get various different responses from each channel's cdr_status register:

1000 0000 = 0x80

1000 0100 = 0x84

0100 0100 = 0x44

0100 0000 = 0x40

0000 0010 = 0x02

0000 0001 = 0x01

0000 0100 = 0x04

0000 0110 = 0x06

To me it seems like we have timeframes where a channel can obtain a lock because the PPM count has been met, and the Single Bit Limit has been reached, but we never can.

I have tried setting/clearing SINGLE_BIT_LIMIT_CHECK_ON (Bit 3 of register 0x0C, and it changes which responses I can get from cdr_status register, but still no lock).

My hunch is that the freerunning VCO frequency is all over the place, as shown by Bits 1:0 in the cdr_status register being unstable.

My next steps would be to hook up the PRBS output to a high frequency scope and try to decode the data rate, or set the multiplexer to output the VCO I-clock and do further tuning.

First, I would like to verify that this setup is even possible.

TLDR: Can a DS125DF410 generate a PRBS signal when free running the VCO, such that another DS125DF410 on another board can lock onto that signal?

Thanks for your help

  • 0
    TI__Mastermind 21725 points

    Hi,

    I'm looking into this and will get back to you by early next week at the latest.

    Best,

    Lucas

  • +1 in reply to Lucas Wolter
    TI__Mastermind 21725 points

    Hi,

    It can sometimes be difficult to generate a PRBS signal at a stable data rate while the VCO is free-running. We typically recommend using the PRBS generator with an input signal that the PRBS sequence can sync to (such as a sub-rate clock signal), but using the PRBS generator with free-running VCO should be possible as well.

    The reason it can be difficult to get a stable data rate with free-running VCO is because the output VCO frequency is set by the CAP DAC and LPF DAC values. These values will vary from part to part, so some tuning is required to obtain the output frequency needed. I recommend directly measuring the VCO frequency while adjusting the CAP DAC and LPF DAC settings until you see a stable frequency.

    Additionally, I want to confirm that you are following the procedure outlined in section 7.5.12 "Using the PRBS Generator" of the datasheet. This section includes detailed instructions on how to configure the PRBS generator while the VCO is free-running.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 10 points

    Lucas,

    Yup! I exactly followed the procedure in section 7.5.12, and dumped my registers after configuration to ensure I had all bits set correctly (especially register 0x09, ensuring bits 7:2 are set as defined in this section). The last paragraph in section 7.5.12 discusses the variability between parts, which you mentioned above as well, and how the VCO can be tuned.

    Unfortunately it looks like I will need to find another solution, because we use numerous boards with these parts, so it would be too much work to individually tune all of them (and I would have to pair up boards, etc. etc.), and likely not be the most reliable system.

    I think for future revisions, it would be a good idea for me to include an onboard reference clock at some subrate of 10.3125 Gbps such that I have the option to switch input, and generate a steady data rate PRBS.

    If I end up getting it working, I will report back, I might try it just to see if it's possible.

    Thanks for helping me investigate this!

    Jon