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DP83848H-MAU-EK: configuration DP83848m/t/H  PHY for   MII mode

Part Number: DP83848H-MAU-EK
Other Parts Discussed in Thread: DP83848M,


I have some problem with DP83848m/t/H   PHY, 

i am usign the devt board : DP83848H-MAU-EK and the communication seems not working

I sent  eth packet with FPGA the MII interface seems to be OK, wut nothing on wireshark ....

the communication  with MDIO/MDC is OK / read back OK

Is it possible to have the whole registers confiugation needed to configure a MII communication ( by registers and set the jumpers of board...)

Thanks in advance.


  • Hi DT,

    Your intuition is correct, I hope I can guide you through this debug. I want to give a fair warning that this is an older part, so support is limited. MDIO/MDC access is good and will help us debug.

    1. Confirm the DP83848 is configured for MII Mode of Operation
      1. I believe the MAU-EK board is configured only for MII Mode
      2. Reading Register 0x17 can confirm this, Bit 5 should be '0'
        1. Reg 0x17 is an Extended Register, I believe to read this register Bit 0 of Reg 0x01 needs to be '1' first.
    2. Check Link Status in Register 0x01, Bit 2
      1. If this bit is high, then the MDI side (cable side) connection is probably okay.

    Typically, if the PHY is configured in the correct MII-Mode (step 1.) and has valid link (step 2.), and there still continues to be communication issues, i.e. no packets seen on wireshark, then the issue might be with the MAC (the FPGA in this case). Please confirm that the FPGA is also correctly configured for MII.



  • Hi Alvaro, 

    Thanks for your reply, i will try it today and come back to you if necesary

    can you support  me regarding the board configuration ? position of jumpers for MII configuration on DP83848H-MAU-EK ??

    it is ambiguous .... 



  • Can you please also confirm if i have to enable MDIX option ( normally yes) and what is the complete configuration for auto negociation ?

    Thanks again , 


  • Hello, 

    i tried to read back the registers, it is normally ok==>  link status is '1' and Mii mode i s enabled

    i put a screenshot example of read back of 0x00 register

    and we noticed that speed 100 mpbs is set but do not understand why the tx clock is 2.5 MHZ instead of 25 Mhz ( seen on screenshot)

    can anyone please give support ? 



  • Hi Dhia,

    We recommend enabling both Auto-MDIX and Auto-Negotiation. This can be confirmed by reading Register 0x0.

    TX_CLK being 2.5 MHz is strange, please read Register 0x10 to confirm the speed that you're in.