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SN65DPHY440SS: I2C command issue with SN65DPHY440SS

Part Number: SN65DPHY440SS

I am evaluating the compatibility between SN65DPHY440SS and our existing MIPI board. I hope to control the enabling of each channel's LP and HS modes through I2C. The register mapping in the datasheet does not seem to be complete. May I ask if there is any SN65DPHY440SS software command that provides the full register mapping? I would appreciate any information on the complete I2C register map and commands for controlling the LP/HS modes of the SN65DPHY440SS  channels.

  • Hello,

    The register map is as indicated in the datasheet. There is not a software command that provides register mapping.



  • Hi,

    You can use the follow I2C write to disable/enable LP/HS mode.

    Write Register 0x50 which is the override enable for HS TX path, bit [7:5] are reserved, bit 4 -> CLK, bit [3:0] -> TX[3:0]

    Write Register 0x51 which disable/ enables HS TX path, bit [7:5] are reserved, bit 4 -> CLK, bit [3:0] -> TX[3:0]

    Write Register 0x61 which disable/enable LP path, bit 7 -> EN_UPSTREAM_LP_TX_D0, bit [4:0] -> LP_TX_CLK, LP_RX_D[3:0]

    Write Register 0x70 which is the override enable for HS RX termination, bit [4:0] -> HS_RX_CLK_TERM, LP_RX_D[3:0]_TERM

    Write Register 0x71 which disables/enable HS RX terminationbit [4:0] -> HS_RX_CLK_TERM, LP_RX_D[3:0]_TERM