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P82B96: Regarding the VOL regulations and IOL regulations regarding P82B96.

Part Number: P82B96

Thank you for your help.

Please tell me about the VOL regulations and IOL regulations regarding P82B96.

Note (5) on page 8 of the P82B96 data sheet contains the following information.

"(5) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the minimum VSx input high level to eliminate any possibility of latching.

" Please tell me the meaning of the above sentence. Does this mean that ``at least 200 μA must flow through the IOL at all times?''

Or is this not a problem as long as the SX terminals of multiple P82B96s are not directly connected?

The characteristics diagram of VOL is shown in Figure 1 and Figure 2 on page 11 of the data sheet.

The data sheet only mentions IOLs of 0.2mA and 3mA, but are there any VOL characteristics for current values between 0.2mA and 3mA?

Also, is it correct to think that the characteristics of VOL depend on the ON resistance of the internal FET and are proportional to the magnitude of the IOL current value?

  • I²C is a bidirectional protocol. Therefore, the P82B96 must be able to detect whether an external device is pulling the line low, even while its own output is pulling low. This is implemented by the P82B96's output driving a higher VOL, and requiring external device to drive to a lower VOL. If the pull-up current is lower than 0.2 mA, this mechanism no longer works.

    The SX terminals of multiple P82B96s must never be connected to each other; see section 9.1.

    You can indeed assume that the output resistance is constant; see [FAQ] What is the output voltage (VOH or VOL) when the output current is X or the supply voltage is Y? But you could simply design your circuit for the I²C limit of 3 mA.

  • Sakamoto-san,

    "(5) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the minimum VSx input high level to eliminate any possibility of latching.

    " Please tell me the meaning of the above sentence. Does this mean that ``at least 200 μA must flow through the IOL at all times?''

    As Clemens was discussing, I2C requires that a device has the capability to communicate in both directions without locking up. P82B96 was designed to detect whether an external device is pulling the line low even when its own output is being pulled low. An external device connected to the output of the P82B96 would need to drive below the VOL set by the P82B96 output which comes out to roughly driving more than 200uA of current. Any current driven <200uA, may result in a LOW logic signal not being able to be passed from the output side to the input side, which is incredibly important for I2C since the controller needs to understand if the downstream target device is receiving communication well. 

    The data sheet only mentions IOLs of 0.2mA and 3mA, but are there any VOL characteristics for current values between 0.2mA and 3mA?

    Also, is it correct to think that the characteristics of VOL depend on the ON resistance of the internal FET and are proportional to the magnitude of the IOL current value?

    We do not have characteristic curves at the moment for IOLs between 0.2mA and 3mA. 

    As Clemens suggested, if the system is designed for the I2C standard at 3mA, any load in between would be handled automatically. 

    Regards,

    Tyler

  • Mr. Clemens, thank you very much for your detailed reply.

    There is something additional that I would like to tell you.

    "Therefore, the P82B96 must be able to detect whether an external device is pulling the line low, even while its own output is pulling low. This is implemented by the P82B96's output driving a higher VOL, and requiring external device to drive to a lower VOL.” I received your answer, but specifically, how does the P82B96 determine whether the external device is LOW? Please tell me the mechanism by which P82B96 can recognize external devices as LOW.

    If the P82B96 outputs LOW and the connected external device is also LOW, a voltage difference will occur, so I don't think the 200μA draw current will occur at the P82B96's Sx terminal. Is it determined whether the connection destination is LOW by "current flows/does not flow to the output and P82B96"?

    Could you please provide me with something like a detailed internal circuit block diagram?

  • Mr. Tyler, thank you very much for your detailed reply.

    Thank you for your explanation. I understand what you explained very well. Thank you for your understanding.

  • The P82B96 does not measure any current; it does measure the voltage at its Sx/Sy pins. When the voltage is lower than VIT (about 0.65 V; see the electrical characteristics), then the low level comes from an external device, and the Tx/Ty pin drives low. When the voltage is higher than VIT, then the signal has a high level, or a low level that comes from the P82B96 itself (VOL is larger than 0.67 V), and Tx/Ty stays inactive.

  • Sakamoto-san,

    Did these responses answer your question fully?

    Regards,

    Tyler

  • Mr. Clemens, thank you very much for your detailed reply.

    I was able to resolve my current question. Also, if you have any questions, we would appreciate your cooperation.

  • Mr. Tyler, thank you very much for your detailed reply.

    I was able to resolve my current question. Also, if you have any questions, we would appreciate your cooperation.

    I would like to end the questions for now.